Associative computer providing semi-parallel architecture

An method of operating an associative memory to provide for associative processing, the associative memory providing a plurality of rows of content addressable memory, each row operating to define stored data and a controller communicating with the rows to search the rows in parallel for a pattern distinct from the sorted data and to write to the rows in parallel according to a pattern distinct from the stored data;

• the method comprising the steps of:
• (a) loading each row with stored data representing two words being addends to be summed, each word including multiple subwords representing successive bits of the words;
• (b) applying search and write cycles in parallel to the subwords using first predetermined patterns to determine whether an addition of the subwords would produce a carry-out bit under both states of an assumed carry-in bit of one and an assumed carry-in bit of zero to determine a contingent carry relationship of each subword, the search and write cycles providing a logical comparison of the first predetermined patterns to the stored data of the subwords to store a result indicating the contingent carry relationships for the subwords;
• (c) applying search and write cycles to the subwords using second predetermined patterns to propagate carry bits through the subwords according to the contingent carry relationship of each subword and a carry-in bit of zero for the least significant subwords, the search and write cycles providing a logical comparison of the second predetermined patterns to the stored data of the subwords to propagate carry bits through the subwords;
• and
• (d) applying search and write cycles on the subwords using third predetermined patterns to add corresponding subwords using the propagated carry bits, the search and write cycles providing a logical comparison of the third predetermined patterns to the stored data of the subwords to add the corresponding carry bits.