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US 10,503,678 B1Granted
Fabric management system and method
AssigneeEMC IP Holding Company LLC
InventorsDaniel Dufresne, Matthew Mullins, Antonio Fontes, Patrick J. Weiler
Life of this patent
Estimating the term…
Abstract
A PCIe fabric is configured to couple a plurality of elements. The PCIe fabric includes a plurality of PCIe subfabrics. A primary master central processing system is configured to couple the plurality of PCIe subfabrics. A secondary master central processing system is configured to couple the plurality of PCIe subfabrics.
Claims12
A Peripheral Component Interconnect Express (PCIe) fabric configured to couple a plurality of elements, the PCIe fabric comprising:
- a plurality of PCIe subfabrics, wherein each of the plurality of PCIe subfabrics includes:
- a managing central processing unit, and
- a PCIe fabric switch;
- a primary master central processing system configured to couple the plurality of PCIe subfabrics and configured to:
- send commands to at least one managing central processing unit of at least one PCIe subfabric of the plurality of PCIe subfabrics;
- and
- a secondary master central processing system configured to couple the plurality of PCIe subfabrics and configured to send commands to at least one managing central processing unit of at least one PCIe subfabric of the plurality of PCIe subfabrics in the event that the primary master central processing system fails;
- wherein the primary master central processing system is configured to determine the topology of the plurality of PCIe subfabrics and determining the topology includes:
- determining the number of managing central processing units included within the PCIe fabric,
- determining the types of elements coupled with the PCIe fabric, and
- providing topological information to the secondary master central processing system.
8 more elements
A Peripheral Component Interconnect Express (PCIe) fabric configured to couple a plurality of elements, the PCIe fabric comprising:
- a plurality of PCIe subfabrics, wherein each of the plurality of PCIe subfabrics includes:
- a managing central processing unit, and
- a PCIe fabric switch;
- a primary master central processing system configured to couple the plurality of PCIe subfabrics and including a primary master central processing unit and a primary fan-out switch configured to electrically couple the primary master central processing unit and the plurality of PCIe subfabrics, wherein the primary master central processing system is configured to send commands to at least one managing central processing unit of at least one PCIe subfabric of the plurality of PCIe subfabrics;
- and
- a secondary master central processing system configured to couple the plurality of PCIe subfabrics configured to electrically couple the secondary master central processing unit and the plurality of PCIe subfabrics, wherein the secondary master central processing system is configured to send commands to at least one managing central processing unit of at least one PCIe subfabric of the plurality of PCIe subfabrics in the event that the primary master central processing system fails;
- wherein the primary master central processing system is configured to determine the topology of the plurality of PCIe subfabrics and determining the topology includes:
- determining the number of managing central processing units included within the PCIe fabric,
- determining the types of elements coupled with the PCIe fabric, and
- providing topological information to the secondary master central processing system.
7 more elements
A Peripheral Component Interconnect Express (PCIe) fabric configured to couple a plurality of elements, the PCIe fabric comprising:
- a plurality of PCIe subfabrics, wherein each of the plurality of PCIe subfabrics includes a managing central processing unit and a PCIe fabric switch;
- a primary master central processing system configured to couple the plurality of PCIe subfabrics and including a primary master central processing unit and a primary fan-out switch configured to electrically couple the primary master central processing unit and the plurality of PCIe subfabrics, wherein the primary master central processing system is configured to send commands to at least one managing central processing unit of at least one PCIe subfabric of the plurality of PCIe subfabrics;
- and
- a secondary master central processing system configured to couple the plurality of PCIe subfabrics and including a secondary master central processing unit and a secondary fan-out switch configured to electrically couple the secondary master central processing unit and the plurality of PCIe subfabrics, wherein the secondary master central processing system is configured to send commands to at least one managing central processing unit of at least one PCIe subfabric of the plurality of PCIe subfabrics in the event that the primary master central processing system fails;
- wherein the primary master central processing system is configured to determine the topology of the plurality of PCIe subfabrics and determining the topology of the plurality of PCIe subfabrics includes:
- determining the number of managing central processing units included within the PCIe fabric,
- determining the types of elements coupled with the PCIe fabric, and
- providing topological information to the secondary master central processing system.
5 more elements
Dependencies are inferred from the claim text.