Semiconductor device including a clock source for generating a clock signal and a clock control circuit for controlling the clock source in hardware, a semiconductor system including the semiconductor device, and a method of operating the semiconductor device

A semiconductor device, comprising:

• a master intellectual property (IP) block which operates in response to a first clock signal provided from a clock management unit (CMU);
• and
• a slave IP block which comprises a function unit which operates in response to a second clock signal provided from the CMU, and an interface unit configured to receive a bus operation signal from the master IP block at a first time point and provide the bus operation signal to the function unit at a second time point different from the first time point,
• wherein the CMU includes a first clock source for providing the first clock signal, the first clock source being controlled by a first clock control circuit, a second clock source for providing the second clock signal, and a third clock source for providing a third clock signal to the first and second clock sources, wherein the first and second clock signals are based on the third clock signal, and
• wherein, in response to a clock stop request from the slave IP block, a second clock control circuit disables the second clock source and transmits a request for clock provision stop to a third clock control circuit that controls the third clock source.

A semiconductor system, comprising:

• a system-on-chip (SoC) comprising:
• a first intellectual property block (IP block) which comprises a function unit and an interface unit;
• a second IP block electrically connected to the first IP block;
• a first clock control circuit which controls a first clock source;
• a second clock control circuit which transmits a first clock request to the first clock control circuit, controls a second clock source which receives a clock signal from the first clock source, and provides the clock signal directly to the first IP block;
• and
• a channel management circuit which transmits a second clock request to the second clock control circuit in response to a clock stop request received from the first IP block, and
• one or more external devices electrically connected to the SoC,
• wherein, in response to the clock stop request from the first IP block, the second clock control circuit disables the second clock source and transmits a request for clock provision stop as the first clock source to the first clock control circuit,
• wherein the function unit controls an operation of the first IP block, and the interface unit receives a first signal provided from the second IP block and provides the first signal to the function unit.