Technique for determining address translation data to be stored within an address translation cache

An apparatus comprising:

• an address translation cache having a plurality of entries, each entry to store address translation data used when converting a virtual address into a corresponding physical address of a memory system;
• control circuitry to perform an allocation process to determine the address translation data to be stored in each entry;
• an interface to receive access requests from a request source, each access request identifying a virtual address;
• and
• prefetch circuitry, responsive to a contiguous access condition being detected from the access requests received by the interface, to retrieve one or more descriptors from a page table, where each descriptor is associated with a virtual page, in order to produce candidate coalesced address translation data relating to multiple contiguous virtual pages, and to trigger the control circuitry to allocate into a selected entry of the address translation cache coalesced address translation data derived from the candidate coalesced address translation data,
• wherein the apparatus is arranged to continue to process access requests from the request source, in parallel with the operation of the prefetch circuitry in the presence of the contiguous access condition.

A method of determining address translation data to be stored within an address translation cache having a plurality of entries, each entry for storing address translation data used when converting a virtual address into a corresponding physical address of a memory system, the method comprising:

• performing an allocation process to determine the address translation data to be stored in each entry;
• receiving access requests from a request source, each access request identifying a virtual address;
• responsive to a contiguous access condition being detected from the received access requests, employing prefetch circuitry to retrieve one or more descriptors from a page table, where each descriptor is associated with a virtual page, in order to produce candidate coalesced address translation data relating to multiple contiguous virtual pages;
• and
• triggering the allocation process to cause the allocation into a selected entry of the address translation cache of coalesced address translation data derived from the candidate coalesced address translation data;
• wherein the prefetch circuitry has associated buffer storage in which a buffer entry is allocated to maintain the candidate coalesced address translation data, and in response to detection of the contiguous access condition, the prefetch circuitry:
• determines for each retrieved descriptor, with reference to the candidate coalesced address translation data, whether coalescing criteria are met by that retrieved descriptor, and in the presence of said coalescing criteria being met, uses that descriptor to update the candidate coalesced address translation data maintained in the buffer entry;
• and
• on a trigger condition, causes the allocation process to store in the selected entry of the address translation cache the coalesced address translation data derived from the candidate coalesced address translation data maintained in the buffer entry.