US 10,503,655 B2Granted

Data block sizing for channels in a multi-channel high-bandwidth memory

AssigneeAdvanced Micro Devices, Inc.

InventorsMitesh R. Meswani, Jee Ho Ryoo

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Abstract

The described embodiments include a computing device that caches data acquired from a main memory in a high-bandwidth memory (HBM), the computing device including channels for accessing data stored in corresponding portions of the HBM. During operation, the computing device sets each of the channels so that data blocks stored in the corresponding portions of the HBM include corresponding numbers of cache lines. Based on records of accesses of cache lines in the HBM that were acquired from pages in the main memory, the computing device sets a data block size for each of the pages, the data block size being a number of cache lines. The computing device stores, in the HBM, data blocks acquired from each of the pages in the main memory using a channel having a data block size corresponding to the data block size for each of the pages.

Claims17

Dependent claims

A computing device, comprising:

a processor;
a main memory;
a high-bandwidth memory (HBM) that is used as a cache by the processor for storing cache lines acquired from the main memory;
and
a plurality of channels coupled between the processor and the HBM, each channel comprising a set of signal routes for accessing data stored in a corresponding portion of the HBM;
wherein the computing device is configured to:
set, for each channel of the plurality of channels, a respective channel data block size, the channel data block size indicating a number of cache lines that are to be included in data blocks that are stored in a portion of the HBM that is accessed via that channel;
set, for pages in the main memory, respective page data block sizes, the page data block size for each of the pages being set based on a record of accesses of cache lines stored in the HBM that were acquired from that page, and the page data block size being a number of cache lines;
select a given channel from among the plurality of channels to be used for storing, in the HBM, data blocks acquired from each of the pages based on a relative size of the page data block size for that page and the channel data block size for each channel;
and
store, in the HBM, data blocks acquired from each of the pages using the given channel for that page.

8 more elements

A method for storing data in a high-bandwidth memory (HBM) used as a cache for data acquired from a main memory in a computing device, the computing device including a plurality of channels coupled between a processor and the HBM, each channel having a set of signal routes for accessing data stored in a corresponding portion of the HBM, the method comprising:

setting, for each channel of the plurality of channels, a respective channel data block size, the channel data block size indicating a number of cache lines that are to be included in data blocks that are stored in a portion of the HBM that is accessed via that channel;
setting, for pages in the main memory, respective page data block sizes, the page data block size for each of the pages being set based on a record of accesses of cache lines stored in the HBM that were acquired from that page, and the page data block size being a number of cache lines;
selecting a given channel from among the plurality of channels to be used for storing, in the HBM, data blocks acquired from each of the pages based on a relative size of the page data block size for that page and the channel data block size for each channel;
and
storing, in the HBM, data blocks acquired from each of the pages using the given channel for that page.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/216,524Filed 21 Jul 2016
Published: US 2018/0024935 A125 Jan 2018
Granted: 10 Dec 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 12/0893
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: caches…
G06F 13/00
Interconnection of, or transfer of information or other signals between, memories, input/output
G06F 2212/1024
Performance improvement: latency reduction
G06F 2212/60
Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures: details of cache memory

Family

US 2018/0024935 A1Pre-grant publication · published 25 Jan 2018
US 10,503,655 B2This patent

From the US filing history. Foreign family members aren’t listed.

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