Sector cache for compression

An electronic device, comprising:

• a central processing unit;
• and
• a general-purpose graphics processing device comprising:
• an instruction cache to receive a stream of instructions;
• an instruction unit to execute the stream of instructions;
• a general-purpose graphics processing compute block comprising a plurality of execution units;
• a shared cache memory communicatively coupled to the plurality of execution units;
• a memory interface communicatively coupled to the shared cache memory comprising a processor to:
• structure the cache memory is structured into a plurality of sectors, each sector in the plurality of sectors comprising at least a first cache line and a second cache line, wherein the first cache line and the second cache line in each of the plurality of sectors are indicated by a pairing bit field assigned by the processor that associates the first cache line and the second cache line with a sector in the plurality of sectors and which is included with cache access operations and in a cache tag field;
• receive a cache access request to the shared cache memory, the cache access request comprising the paring bit field;
• and
• use the pairing bit field to locate the at least a first cache line and a second cache line associated with the cache access request to the shared cache memory;
• and
• a data compression unit communicatively coupled to the cache memory, wherein the data compression unit operates at a sector-level granularity.