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US 10,503,649 B2Granted
Integrated circuit and address mapping method for cache memory
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorShih-Lien Linus Lu
Life of this patent
Estimating the term…
Abstract
An integrated circuit (IC) is provided. The IC includes a cache memory and an address decoder. The cache memory is divided into a plurality of groups. The address decoder provides a physical address according to an access address. When the access address corresponds to a specific group of the groups of the cache memory, the address decoder changes the access address to provide the physical address, and when the access address corresponds to one of the groups other than the specific group in the cache memory, the address decoder assigns the access address as the physical address.
Claims20
An address mapping method of a cache memory, comprising:
- dividing the cache memory into a plurality of groups, wherein each of the groups comprises a plurality of sets;
- assigning the groups in rotation for a plurality of time periods, wherein each of the groups is assigned in a corresponding single one of the time periods,
- determining whether an access address of the cache memory corresponds to the assigned group of the groups of the cache memory, so as to provide providing a control signal;
- providing a mapping address to the assigned group of the cache memory when the control signal indicates that the access address corresponds to the assigned group of the groups of the cache memory;
- and
- providing the access address to an unassigned group of the cache memory when the control signal indicates that the access address corresponds to the unassigned group in the cache memory, wherein the unassigned group of the cache memory is one of the groups other than the assigned group in the cache memory,
- wherein configuration of the sets of the assigned group is different from that of the sets of the groups other than the assigned group in the cache memory,
- wherein the sets of the assigned group that is assigned in a first time period are not overlapping with the sets of other assigned groups that are assigned in the time periods other than the first time period.
5 more elements
An integrated circuit (IC), comprising:
- a cache memory divided into a plurality of groups, wherein each of the groups comprises a plurality of sets, and one of the groups is assigned as a first group and the remaining groups are assigned as a plurality of second groups, wherein the first group and the second groups are assigned in rotation for a plurality of time periods, and each of the groups is assigned in a corresponding single one of the time periods;
- and
- an address decoder, comprising:
- a controller configured to determine whether an access address of the cache memory corresponds to the first group of the groups of the cache memory, so as to provide a control signal;
- and
- a multiplexer coupled between the controller and the cache memory, and configured to selectively provide the access address or a mapping address as a physical address according to the control signal,
- wherein when the control signal indicates that the access address corresponds to the first group of the groups of the cache memory, the multiplexer is configured to provide the mapping address as the physical address corresponding to the first group, and when the control signal indicates that the access address corresponds to one of the second groups in the cache memory, the multiplexer is configured to provide the access address as the physical address corresponding to the one of the second groups,
- wherein the sets in the first group of the cache memory have an adjustable configuration, and the sets in each of the second groups of the cache memory have a regulation configuration,
- wherein the sets of the first group that is assigned in a first time period are not overlapping with the sets of other first groups that are assigned in the time periods other than the first time period.
6 more elements
An integrated circuit (IC), comprising:
- a cache memory divided into a plurality of groups, wherein each of the groups comprises a plurality of sets;
- a processor, providing a first control signal to assign one of the groups in a specific sequence for a plurality of time periods, wherein each of the groups is assigned in a corresponding single one of the time periods;
- and
- an address decoder, receiving an access address of the cache memory and comprising:
- a controller configured to determine whether the access address corresponds to the assigned group of the groups of the cache memory, so as to provide a second control signal;
- and
- a multiplexer coupled between the controller and the cache memory, and configured to selectively provide the access address or a mapping address to the cache memory according to the second control signal,
- wherein when the second control signal indicates that the access address corresponds to the assigned group of the groups of the cache memory, the multiplexer is configured to provide the mapping address to the assigned group in the cache memory,
- wherein when the second control signal indicates that the access address corresponds to an unassigned group of the cache memory, the multiplexer is configured to provide the access address to the unassigned group of the cache memory, and the unassigned group of the cache memory is one of the groups other than the assigned group in the cache memory,
- wherein configuration of the sets of the assigned group is different from that of the sets of the groups other than the assigned group in the cache memory,
- wherein the sets of the assigned group that is assigned in a first time period are not overlapping with the sets of other assigned groups that are assigned in the time periods other than the first time period.
8 more elements
Dependencies are inferred from the claim text.