Cache allocation based on quality-of-service information
AssigneeSamsung Electronics Co., Ltd.
InventorMoon Gyung Kim
Life of this patent
Estimating the term…
Abstract
A cache memory device shared by a plurality of processors includes a cache memory configured to store some of data stored in a main memory and to be accessed by the plurality of processors. A cache controller stores quality-of-service (QoS) information of each of the plurality of processors and differently sets a size of a storage space of the cache memory to be managed by a target processor, based on the QoS information of the target processor.
Claims15
A system-on-chip comprising:
- a first processor;
- a second processor;
- a cache memory configured to store quality-of-service (QoS) information of each of the first and second processors;
- and
- a cache controller configured to differently set a size of a storage space of the cache memory to be managed by each of the first and second processors, based on the QoS information of each of the first and second processors, wherein:
- the cache memory comprises a plurality of entries,
- the plurality of entries is divided into two or more entry groups,
- the cache controller limits an entry group to be accessed among the two or more entry groups, based on cache size information corresponding to the QoS information, and
- when the QoS information of any of the first and second processors is changed, the cache controller sets the size of the storage space of the cache memory based on the changed QoS information.
A cache memory device shared by a plurality of processors, the cache memory device comprising:
- a cache memory configured to store quality-of-service (QoS) information of each of the plurality of processors;
- and
- a cache controller configured to allocate a size of a storage space of the cache memory to be managed by a target processor, based on the QoS information of the target processor, wherein
- a number of the plurality of processors is equal to or greater than ‘2’, wherein:
- the cache memory comprises a plurality of entries,
- the cache controller further comprises:
- an entry manager configured to provide an available entry list based on cache size information corresponding to the QoS information, and
- an entry allocator configured to allocate a new entry or replace an existing entry, among the plurality of entries, with another entry according to the available entry list, and
- when the QoS information of any of the plurality of processors is changed, the cache controller sets the size of the storage space of the cache memory based on the changed QoS information.
A method, executed by a cache memory controller, of allocating memory of a cache, shared in common by multiple processors, to each of the processors, the method comprising:
- receiving, from each of the processors, an electronic communication comprising an indication of the processor's identification;
- identifying, for each processor based upon the indication of the processor's identification, quality-of-service (QoS) information identifying a QoS required by the processor;
- allocating memory of the cache to each of the processors in accordance with the identified QoS information for the processor;
- determining whether a data request from a first of the processors is stored in the memory allocated to the first processor;
- determining whether the memory allocated to the first processor should be expanded;
- allocating additional memory to the first processor, upon determining that the memory allocated to the first processor should be expanded;
- and
- when the QoS information is changed, allocating memory of the cache to each of the processors in accordance with the change QoS information for the processor.
Dependencies are inferred from the claim text.