Selective data retrieval based on access latency

A method, comprising:

• identifying, at a first cache associated with a first processor core, a first cache miss at a first time and in response to a first memory access request targeting first data associated with a first memory address;
• in response to the first cache miss:
• identifying a first latency associated with retrieving the first data from a second cache associated with a second processor core;
• and
• in response to identifying that the first latency exceeds a first threshold, providing the first memory access request to a system memory associated with the first processor core and the second processor core;
• identifying, at the first cache, a second cache miss at a second time and in response to a second memory access request targeting second data associated with a second memory address;
• in response to the second cache miss:
• identifying a second latency associated with retrieving the second data from the second cache, the second latency different from the first latency;
• and
• in response to identifying that the second latency is less than the first threshold, satisfying the second memory access request at the second cache.

A processor, comprising:

• a plurality of processor cores including a first processor core and a second processor core;
• a plurality of caches, including a first cache associated with the first processor core and a second cache associated with the second processor core, the first cache to:
• in response to a first memory access request targeting first data associated with a first memory address, identify a first cache miss;
• and
• a coherency manager to:
• in response to the first cache miss, identify a first latency associated with retrieving the first data from the second cache;
• and
• in response to identifying that the first latency exceeds a first threshold, provide the first memory access request to a system memory associated with the first processor core and the second processor core.