Memory system and SoC including linear remapper and access window

A mobile electronic device comprising:

• a display panel configured to display image data;
• an RF transceiver unit configured to perform wireless data communications;
• a plurality of memory chips configured to store data;
• and
• an application processor connected to the display panel, the RF transceiver unit, and the plurality of memory chips, wherein:
• the application processor includes:
• first and second processors configured to provide an address for using the plurality of memory chips;
• a first access window configured to set an area, accessed only by the first processor, from among address areas of one or more of the plurality of memory chips;
• a first linear remapper configured to generate a linear-access memory map from addresses within the area that are received from the first processor;
• and
• a memory controller configured to perform a partial linear access operation with respect to the plurality of memory chips, based on the area set by the first access window and the linear-access memory map, wherein:
• the first linear remapper generates the linear-access memory map by remapping, for each of the memory chips, consecutively increasing memory addresses of the memory chip, within an interleaved-access memory map, to monotonically increasing memory addresses for accessing a first of the memory chips,
• the memory controller applies the partial linear access operation to the first memory chip so as to sequentially access consecutive memory addresses of the first memory chip within the linear-access memory map, and
• each of any two consecutive memory addresses within the interleaved-access memory map addresses a different one of the memory chips.

A method of accessing memory chips, the method comprising:

• accessing, with a first processor, a first memory area within each of the memory chips through an interleaved access operation;
• generating a linear-access memory map by remapping, for each of the memory chips, consecutively increasing memory addresses of the memory chip, within an interleaved-access memory map, to monotonically increasing memory addresses for accessing a second memory area within a first of the memory chips through a linear access operation;
• and
• accessing, solely with a second processor, the second memory area within the first memory chip solely through the linear access operation so as to sequentially access consecutive memory addresses of the first memory chip within the linear-access memory map, wherein:
• each of any two consecutive memory addresses within the interleaved-access memory map addresses a different one of the memory chips, and
• the second memory area is a same size or larger than the first memory area.

A memory system that accesses memory chips, the system comprising:

• a first processor that accesses a first memory area within each of the memory chips through an interleaved access operation;
• a linear remapping component that generates a linear-access memory map by remapping, for each of the memory chips, consecutively increasing memory addresses of the memory chip, within an interleaved-access memory map, to monotonically increasing memory addresses for accessing a second memory area within a first of the memory chips through a linear access operation;
• and
• a second processor that solely accesses the second memory area within the first memory chip solely through the linear access operation so as to sequentially access consecutive memory addresses of the first memory chip within the linear-access memory map, wherein:
• each of any two consecutive memory addresses within the interleaved-access memory map addresses a different one of the memory chips, and
• the second memory area is a same size or larger than the first memory area.