Time-based on-chip hardware performance monitor

A distributed performance monitoring circuit, comprising:

• a plurality of performance monitors, each performance monitor corresponding to a respective functional block of a system and including a counter circuit, wherein the counter circuit includes:
• a programmable time window counter configured to determine an adjustable counting period;
• and
• an event counter configured to count a number of occurrences of an event occurring in the respective functional block during the counting period, the event being a type of activities occurring in the respective functional block;
• and
• a cross-trigger network coupled to the plurality of performance monitors, wherein the cross-trigger network is configured to:
• receive an output trigger signal from a performance monitor of the plurality of performance monitors when the number of occurrences of the event occurring in the corresponding functional block during the counting period is outside of a threshold band for the performance monitor;
• and
• send an input trigger signal to the plurality of performance monitors based on receiving the output trigger signal.