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US 10,503,593 B2Granted
Two layer quad bit error correction
AssigneeEverspin Technologies, Inc.
InventorKurt Baty
Life of this patent
Estimating the term…
Abstract
In some examples, a memory device may be configured to provide quad bit error correction circuits. For example, the memory device may be equipped with a two layer error correction circuit. In some cases, the first layer may utilized one or more Hamming coders and the second layer may utilize one or Golay coders. In some examples, the Golay coders may be grouped into sets of Golay coders.
Claims20
An error correction circuit, comprising:
- a first layer, the first layer comprising one or more Hamming coders, wherein each Hamming coder of the one or more Hamming coders is configured to process data to generate a Hamming code, wherein the Hamming code comprises the data and Hamming code bits;
- and
- a second layer, the second layer comprising one or more sets of Golay coders, wherein at least one set of Golay coders is configured to process the data to generate a corresponding Golay code, wherein the Golay code comprises the data and Golay code bits,
- wherein one of the first layer or the second layer is configured to correct errors within the data missed by the other of the first layer or the second layer based on the Hamming code and the Golay code, causing the error correction circuit to correct quad bit errors.
1 more element
A method comprising:
- receiving, by a memory device, data to be stored in one or more memory arrays of the memory device;
- processing, by each of one or more Hamming coders, the data to generate a Hamming code, wherein the Hamming code comprises the data and Hamming code bits;
- processing, by at least one set of one or more sets of Golay coders, the data to generate a Golay code, wherein the Golay code comprises the data and Golay code bits;
- and
- correcting, based on the Hamming code and the Golay code, a quad bit error, wherein one of (i) the each of the one or more Hamming coders or (ii) the at least one set of one or more sets of Golay coders is configured to correct errors within the data missed by the other of (i) the each of the one or more Hamming coders and (ii) the at least one set of one or more sets of Golay coders.
2 more elements
An error correction circuit, comprising:
- a first layer comprising one or more Hamming coders, wherein each Hamming coder of the one or more Hamming coders is configured to:
- receive data bits to be stored in one or more memory arrays,
- generate a first set of Hamming code bits based on the received data bits, and
- store the first set of Hamming code bits in the one or more memory arrays;
- and
- a second layer comprising one or more sets of Golay coders, wherein each set of the one or more sets of Golay coders is configured to:
- receive a portion of the data bits to be stored in the one or more memory arrays,
- generate a first set of Golay code bits based on the received portion of the data bits, and
- store the first set of Golay code bits in the one or more memory arrays,
- wherein one of the first layer or the second layer is configured to correct errors within the data bits missed by the other of the first layer or the second layer based on the first set of Hamming code bits and the first set of Golay code bits, causing the error correction circuit to correct quad bit errors.
7 more elements
Dependencies are inferred from the claim text.