Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices

A memory system comprising:

• at least one semiconductor memory device;
• and
• a memory controller configured to control the at least one semiconductor memory device,
• wherein the at least one semiconductor memory device comprises:
• a memory cell array;
• an error correction circuit;
• an input/output gating circuit (I/O gating circuit) connected between the error correction circuit and the memory cell array;
• and
• a control logic circuit configured to generate control signals by decoding a command received from the memory controller,
• wherein the control logic circuit is, in a first write operation mode, configured to control the I/O gating circuit and the error correction circuit such that:
• the I/O gating circuit is configured to select a sub-page of a target page, to read a first unit of data including (i) a first sub unit of data, (ii) a second sub unit of data and (iii) a first parity data from the sub-page and configured to provide the first unit of data to the error correction circuit, and
• the error correction circuit is configured to perform an error-correcting code (ECC) decoding on the first unit of data to generate syndrome data, to generate second parity data based on a portion of the first unit of data and to generate third parity data based on a write parity data, the second parity data and the syndrome data, wherein the write parity data is provided from the memory controller and is associated with main data to be written in the sub-page.

A method of operating a semiconductor memory device including a memory cell array, the method comprising:

• receiving a command, an address, main data, a data mask signal and write parity data associated with the main data from an external memory controller;
• generating second parity data and check bits based on a portion of a first unit of data including (i) a first sub unit of data, (ii) a second sub unit of data and (iii) first parity data read from a memory region corresponding to the address;
• generating syndrome data based on the first parity data and the check bits;
• generating third parity data based on the write parity data, the second parity data and the syndrome data;
• and
• writing the main data and the third parity data in the memory region corresponding to the address,
• wherein the second parity data is generated based on one of the first sub unit of data and the second sub unit of data in response to the data mask signal.