Low cost, hardened single board computer for command and data handling
AssigneeTriad National Security, LLC
InventorsRobert Bernard Merl, Paul Stanley Graham
Life of this patent
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Abstract
A radiation hardened single board computer (SBC) includes a processor; static random-access memory (SRAM); non-volatile memory; a field programmable gate array (FPGA); and board-level physical layer interfaces.
Claims20
A radiation hardened single board computer (SBC) comprising:
- a processor;
- static random-access memory (SRAM);
- non-volatile memory;
- a field programmable gate array (FPGA);
- and
- board-level physical layer interfaces, wherein the SBC is configured to interface with one or more sensor boards not located within the SBC via the board-level physical layer interfaces, wherein each of the sensor boards comprises an FPGA comprising SRAM programming memory, and
- wherein the FPGA of the SBC is configured to perform automated error detection and correction for errors found in the SRAM programming memory of each of the FPGAs of the one or more sensor boards.
A field programmable gate array (FPGA) of a radiation hardened single board computer (SBC) configured to provide a platform for custom hardware co-processing functions to reduce a load on a processor application-specific integrated circuit (ASIC) of the SBC, the FPGA comprising:
- physical layer support for interfaces,
- wherein the SBC is configured to interface with a sensor board not located within the SBC, and
- wherein the FPGA of the radiation hardened SBC is configured to perform automated error detection and correction for errors found in static random access memory (SRAM) configuration memory of an FPGA of the sensor board.
A method of providing error detection and correction by a field programmable gate array (FPGA) and processor of a radiation hardened single board computer (SBC), the error detection and correction being for an instrument board not located within the SBC, the method comprising:
- detecting, at the FPGA, an error in a configuration memory of the instrument board;
- interrupting a processor of the instrument board, by the FPGA, when the error is detected;
- and
- fixing, by the processor, the error in the configuration memory of the instrument board.
A radiation hardened single board computer (SBC) comprising:
- a processor;
- static random-access memory (SRAM);
- non-volatile memory;
- a field programmable gate array (FPGA);
- and
- board-level physical layer interfaces, wherein the SBC is configured to interface with one or more sensor boards via the board-level physical layer interfaces,
- wherein the FPGA is configured to perform automated error detection and correction for errors found in a plurality of SRAM programming memory of FPGAs of the sensor boards, and
- wherein the SBC consumes 6.6 W or less.
Dependencies are inferred from the claim text.