Back to results
US 10,503,552 B1Granted
Scheduler for vector processing operator readiness
AssigneeAmbarella, Inc.
InventorPeter Verplaetse
Life of this patent
Estimating the term…
Abstract
An apparatus includes a plurality of hardware engines and a scheduler circuit. The hardware engines may be configured to process a plurality of vectors using a plurality of operators. The scheduler circuit may be configured to (i) parse a directed acyclic graph into one or more of the operators, (ii) determine a readiness of each of the operators and (iii) schedule the one or more operators in at least one of the hardware engines based on the readiness. The scheduler circuit may be implemented solely in hardware.
Claims20
An apparatus comprising:
- a plurality of hardware engines configured to process a plurality of vectors using a plurality of operators;
- a scheduler circuit configured to (i) parse a directed acyclic graph into one or more of said operators and (ii) schedule said one or more operators in at least one of said hardware engines based on one or more status signals indicating a readiness state of the one or more operators;
- and
- an operator readiness circuit implemented solely in hardware and configured to (i) store target and actual positions for operands of the one or more operators in a plurality of tables, (ii) compare a target position and an actual position of each operand associated with the one or more operators to determine a readiness state of each operand, (iii) update said readiness state of said operands using a plurality of state machines each time one or more positions in the plurality of tables are modified, and (iv) generate said one or more status signals indicating said readiness state of the one or more operators based on the readiness state of each operand associated with said one or more operators.
1 more element
A method for scheduling operators, comprising the steps of:
- parsing a directed acyclic graph into one or more operators using a scheduler circuit comprising an operator readiness circuit implemented solely in hardware;
- storing target and actual positions for operands of the one or more operators in a plurality of tables;
- utilizing said operator readiness circuit to (i) compare a target position and an actual position of each operand associated with the one or more operators to determine a readiness state of each operand, (ii) update said readiness state of said operands using a plurality of state machines each time one or more positions in the plurality of tables are modified, and (iv) generate one or more status signals indicating a readiness state of the one or more operators based on the readiness state of each operand associated with said one or more operators;
- scheduling said one or more operators in at least one of a plurality of hardware engines based on said one or more status signals indicating said readiness state of the one or more operators;
- and
- processing a plurality of vectors using said operators in said at least one hardware engine.
3 more elements
Dependencies are inferred from the claim text.