US 10,503,542 B2Granted

Systems, methods and devices for work placement on processor cores

AssigneeIntel Corporation

InventorsGuy Therien, Guy Sotomayor, Arijit Biswas, Michael D. Powell, Eric J. Dehaemer

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Abstract

Work can be migrated between processor cores. For example, a thread causing a heavy load on a first core can be detected. A power control unit can determine to migrate the thread from the first less-efficient core to the second more-efficient core. The power control unit can request that the first core and the second core transition to a low-power state (e.g., a sleep state, a C6 power state, etc.). The first core can transfer its software context to a first core software context storage, halt and quiesce. The second core can halt and quiesce. The software context from the first core software context storage can be transferred to a second core software context storage of the second core. A processing core identifier of the first core can be assigned to the second core. The power control unit can then request the second core to transition to an active state (such as a C0 state).

Claims9

Dependent claims

A non-transitory computer-readable storage medium that stores instructions for execution by a processing resource to perform operations of a power control unit within a processor, the operations, when executed by the processing resource, to perform a method, the method comprising to:

report fewer processing cores to an operating system than are present within the processor;
assign a first identifier to a first processing core within the processor and a second identifier to a second processing core within the processor;
detect a migration trigger that indicates detection of an instruction that would use a broken arithmetic unit on a first core;
determine to sequester the first processing core from use by the operating system and migrate a thread from the first processing core to the second processing core;
transmit a sleep transition message to the first processing core and the second processing core, the sleep transition message requesting a transition to a low-power state, the low-power state causing the first processing core to save a first context in a first processor context storage;
copy the first context from the first processor context storage to an intermediate storage;
copy the first context from the intermediate storage to a second processor context storage;
assign the first identifier to the second processing core;
sequester the first processing core from use by the operating system;
transmit a wake-up transition message to the second processing core, the wake-up transition message requesting a transition to an active state, the transition causing the second processing core to resume the first context from the second processor context storage and the second processing core to resume the first context from the second processor context storage;
and
run a diagnostic sequence on the sequestered first processing core.

9 more elements

A non-transitory computer-readable storage medium that stores instructions for execution by a processing resource to perform operations of a processor with multiple cores, the operations, when executed by the processing resource, to perform a method, the method comprising to:

report fewer processing cores to an operating system than are present within the processor;
detect a migration trigger that indicates detection of a broken arithmetic unit on a first core;
transmit a migration signal to the first core and a second core;
transition the first core to a sleep state, including:
save a first core software context to a first core context storage;
and
enter the first core into a sleep state in which the first core is quiesced and halted;
transition the second core to a sleep state, including:
enter the second core into a sleep state in which the second core is quiesced and halted;
transfer a core identity from the first core to the second core;
sequester the first core from use by the operating system;
transfer the first core software context from the first core software context storage to a second core software context storage;
wherein transferring the first processor software context from the first core software context storage to a second core software context storage comprises:
copying the first core software context from the first core context storage and the second core software context from the second core context storage to an intermediate storage;
and
copying the first core software context from the intermediate storage to the second core software context storage and the second core software context from the intermediate storage to the first core software context storage;
and
transmit a resume signal to the second core;
transition the second core from the sleep state to an active state, including:
restore the first core software context to the second core from the second core software context storage;
and
run a diagnostic sequence on the sequestered first processing core.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/048,570Filed 30 Jul 2018 · continuation
Priority: 17 Dec 2015
Published: US 2019/0065242 A128 Feb 2019
Granted: 10 Dec 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G06F 9/4856
Task life-cycle, e.g. stopping, restarting, resuming execution: resumption being on a different machine, e.g. task migration, virtual machine…
G06F 1/3287
Power saving characterised by the action undertaken: by switching off individual functional units in the computer system
G06F 9/4418
Bootstrapping: suspend and resume; Hibernate and awake
G06F 9/461
Multiprogramming arrangements: saving or restoring of program or task context

Family

Application14/973,009Parent of this continuation · filed 17 Dec 2015
US 2019/0065242 A1Pre-grant publication · published 28 Feb 2019
US 10,037,227 B2Parent of this continuation
US 2017/0177407 A1Published application
US 10,503,542 B2This patent

From the US filing history. Foreign family members aren’t listed.

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