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US 10,503,538 B2Granted
Delaying branch prediction updates specified by a suspend branch prediction instruction until after a transaction is completed
AssigneeInternational Business Machines Corporation
InventorsMichael K Gschwind, Valentina Salapura
Life of this patent
Estimating the term…
Abstract
In a branch predictor in a processor capable of executing transactional memory transactions, the branch predictor speculatively predicts the outcome of branch instructions, such as taken/not-taken, the target address and the target instruction. Branch prediction information is buffered during a transaction, and is only loaded into the branch predictor when the transaction is completed. The branch prediction information is discarded if the transaction aborts.
Claims12
A computer system for delaying branch prediction updates in a transaction of a transactional memory (TM) environment, the computer system comprising:
- a memory;
- and
- a processor in communication with the memory, the processor comprising a branch predictor and a prediction buffer, wherein the computer system is configured to perform a method, the method comprising:
- executing first branch instructions, by the processor, in a non-transactional execution mode, the executing using the branch predictor for predicting an outcome of the first branch instructions;
- updating the branch predictor based on the execution of the first branch instructions;
- entering a transactional execution (TX) mode for executing the transaction;
- executing second branch instructions of the transaction in the TX mode;
- based on being in the TX mode, suppressing branch prediction information updates to the branch predictor for the executed second branch instructions and buffering branch prediction information for the executed second branch instructions in the prediction buffer;
- determining that the transaction has completed;
- and
- based on the transaction being completed, updating the branch predictor with the buffered branch prediction information from the prediction buffer and exiting the TX mode,
- wherein the processor comprises a suppression indicator, the suppression indicator to indicate whether the processor is processing in branch suppression mode and being separate from a transaction state indicator that indicates whether the processor is executing in transactional execution mode, and the suppression indicator configured to have a first state indicating no suppression of updates to the branch predictor and a second state indicating suppression of updates to the branch predictor, wherein the method further comprises:
- setting the suppression indicator to the second state based on being in the transaction and executing a suspend branch prediction instruction separate from a transaction begin instruction to suppress specified updates to the branch predictor, the specified updates being suppressed being indicated by the suspend branch prediction instruction;
- and
- setting the suppression indicator to the first state upon completing the transaction to enable updates to the branch predictor.
12 more elements
A computer program product for delaying branch prediction updates in a transaction of a transactional memory (TM) environment, the computer program product comprising:
- a non-transitory computer-readable storage medium, readable by a processor and storing instructions for execution by the processor for performing a method comprising:
- executing first branch instructions, by the processor, in a non-transactional execution mode, the executing using a branch predictor for predicting an outcome of the first branch instructions;
- updating the branch predictor based on the execution of the first branch instructions;
- entering a transactional execution (TX) mode for executing the transaction;
- executing second branch instructions of the transaction in the TX mode;
- based on being in the TX mode, suppressing branch prediction information updates to the branch predictor for the executed second branch instructions and buffering branch prediction information for the executed second branch instructions in a prediction buffer;
- determining that the transaction has completed;
- and
- based on the transaction being completed, updating the branch predictor with the buffered branch prediction information from the prediction buffer and exiting the TX mode,
- wherein the processor comprises a suppression indicator, the suppression indicator to indicate whether the processor is processing in branch suppression mode and being separate from a transaction state indicator that indicates whether the processor is executing in transactional execution mode, and the suppression indicator configured to have a first state indicating no suppression of updates to the branch predictor and a second state indicating suppression of updates to the branch predictor, wherein the method further comprises:
- setting the suppression indicator to the second state based on being in the transaction and executing a suspend branch prediction instruction separate from a transaction begin instruction to suppress specified updates to the branch predictor, the specified updates being suppressed being indicated by the suspend branch prediction instruction;
- and
- setting the suppression indicator to the first state upon completing the transaction to enable updates to the branch predictor.
10 more elements
A computer-implemented method for delaying branch prediction updates in a transaction of a transactional memory (TM) environment, the method comprising:
- executing first branch instructions, by a processor, in a non-transactional execution mode, the executing using a branch predictor for predicting an outcome of a the first branch instructions;
- updating the branch predictor based on the execution of the first branch instructions;
- entering a transactional execution (TX) mode for executing the transaction;
- executing second branch instructions of the transaction in the TX mode;
- based on being in the TX mode, suppressing branch prediction information updates to the branch predictor for the executed second branch instructions and buffering branch prediction information for the executed second branch instructions in a prediction buffer;
- determining that the transaction has completed;
- and
- based on the transaction being completed, updating the branch predictor with the buffered branch prediction information from the prediction buffer and exiting the TX mode,
- wherein the processor comprises a suppression indicator, the suppression indicator to indicate whether the processor is processing in branch suppression mode and being separate from a transaction state indicator that indicates whether the processor is executing in transactional execution mode, and the suppression indicator configured to have a first state indicating no suppression of updates to the branch predictor and a second state indicating suppression of updates to the branch predictor, wherein the method further comprises:
- setting the suppression indicator to the second state based on being in the transaction and executing a suspend branch prediction instruction separate from a transaction begin instruction to suppress specified updates to the branch predictor, the specified updates being suppressed being indicated by the suspend branch prediction instruction;
- and
- setting the suppression indicator to the first state upon completing the transaction to enable updates to the branch predictor.
9 more elements
Dependencies are inferred from the claim text.