Method for implementing a reduced size register view data structure in a microprocessor

A computer system configured to implement a method of managing a reduced size register view data structure, the computer system comprising:

• a memory to store a set of instructions;
• and
• a processor coupled to the memory, the processor including a set of execution units, a global front end to receive an incoming instruction sequence and to group instructions from the incoming instruction sequence to form instruction blocks, and a scheduler to schedule execution of the instruction blocks to the set of execution units, the scheduler including a register view data structure, the scheduler to populate a register view data structure, wherein the register view data structure stores register information references by the instruction blocks as a set of register templates, to generate a set of snapshots of the register templates to reduce a size of the register view data structure, and to track a state of the processor to handle a branch miss-prediction using the register view data structure in accordance with execution of the instruction blocks.