SM3 hash function message expansion processors, methods, systems, and instructions

A method in a processor, the method comprising:

• receiving an instruction, the instruction indicating a first source packed data operand and indicating a second source packed data operand, wherein a field of the instruction explicitly specifies an architectural packed data register of the processor which stores one of the first and second source packed data operands, the first and second source packed data operands each including a plurality of data elements, the data elements of the first and second source packed data operands including information selected from messages and logical combinations of messages that is sufficient to evaluate:
• P1(Wj−16 XOR Wj−9 XOR (Wj−3<<<15)) XOR (Wj−13<<<7) XOR Wj−6,
• in which P1 is a permutation function:
• P1(X)=X XOR (X<<<15) XOR (X<<<23),
• in which Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6 are messages associated with a compression function of an SM3 hash function, in which XOR is an exclusive OR operation, and in which <<< is a rotate operation, wherein said one of the first and second source packed data operands includes a first data element at a first position in the architectural packed data register, the first data element equal to a logical combination of a subset of the messages Wj−16, Wj−9, Wj−3, W−13, and Wj−6;
• and
• storing a result packed data in the architectural packed data register the result packed data including a Wj message to be input to a round j of the compression function of the SM3 hash function,
• wherein the instruction implicitly indicates that the architectural packed data register is also used to store the result packed data,
• wherein the Wj message is stored at the first position in the architectural packed data register overwriting the logical combination of the subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6, and
• wherein the result packed data also stores the message Wj−6.

A processor comprising:

• a plurality of packed data registers;
• a decode unit to decode an instruction, the instruction to indicate a first source packed data operand and to indicate a second source packed data operand, wherein the instruction has a field to explicitly specify a first packed data register of the plurality of packed data registers which is to store one of the first and second source packed data operands, the first and second source packed data operands each to include a plurality of data elements, the data elements of the first and second source packed data operands to include messages Wj−16, Wj−15, Wj−9, Wj−8, Wj−3, and Wj−2 associated with a compression function of an SM3 hash function, the data elements of the first and second source packed data operands to also include a first data element equal to a first combination W*j−6 which is to be equal to (Wj−13<<<7) XOR Wj−6, and a second data element equal to a second combination W*j−5 which is to be equal to (Wj−12<<<7) XOR Wj−5, where Wj−13, Wj−12, Wj−6, and Wj−5 are also messages associated with the compression function, wherein said one of the first and second source packed data operands is to include at least one of the first and second data elements at a first position in the first packed data register;
• and
• an execution unit coupled with the decode unit, the execution unit operable, in response to the instruction, to store a result packed data in the first packed data register, the result packed data to include a Wj message to be input to a round j of the compression function, and a Wj+1 message to be input to a round j+1 of the compression function,
• wherein the first packed data register is implicitly to be used to store the result packed data,
• wherein the Wj message is to be stored at the first position in the first packed data register overwriting said one of the first and second data elements.

A system to process instructions comprising:

• an interconnect;
• a processor coupled with the interconnect, the processor having a plurality of packed data registers, the processor to receive an instruction that is to indicate a first source packed data operand and to indicate a second source packed data operand, the instruction having a field to explicitly specify a first packed data register of the plurality of packed data registers which is to store one of the first and second source packed data operands, the first and second source packed data operands each to include a plurality of data elements, the data elements of the first and second source packed data operands to include information selected from messages and logical combinations of messages that is sufficient to evaluate:
• P1(Wj−16 XOR Wj−9 XOR (Wj−3<<<15)) XOR (Wj−13<<<7) XOR
• in which P1 is a permutation function:
• P1(X)=X XOR (X<<<15) XOR (X<<<23),
• in which Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6 are messages associated with a compression function of an SM3 hash function, in which XOR is an exclusive OR operation, and in which <<< is a rotate operation, wherein said one of the first and second source packed data operands is to include a first data element at a first position in the first packed data register, the first data element to be equal to a logical combination of a subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6, the processor operable, in response to the instruction, to store a result packed data in the first packed data register the result packed data to include a Wj message to be input to a round j of the compression function of the SM3 hash function, wherein the instruction is to implicitly indicate that the first packed data register is also to be used to store the result packed data, and wherein the Wj message is to be stored at the first position in the first packed data register overwriting the logical combination of the subset of the messages Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6;
• and
• a dynamic random access memory (DRAM) coupled with the interconnect.

A processor comprising:

• a plurality of packed data registers;
• a decode unit to decode an instruction that is to indicate a first source packed data operand and to indicate a second source packed data operand, wherein the instruction has a field to explicitly specify a packed data register of the plurality of packed data registers which is to store one of the first and second source packed data operands, the first and second source packed data operands each to include a plurality of data elements, the data elements of the first and second source packed data operands to include information selected from messages and logical combinations of messages associated with an SM3 hash function that is sufficient to evaluate:
• P1(Wj−16 XOR Wj−9 XOR (Wj−3<<<15)) XOR (Wj−13<<<7) XOR Wj−6,
• in which P1 is a permutation function P1(X)=X XOR (X<<<15) XOR (X<<<23), Wj−16, Wj−9, Wj−3, Wj−13, and Wj−6 are messages associated with a compression function of the SM3 hash function, XOR is an exclusive OR operation, and <<< is a rotate operation;
• and
• an execution unit coupled with the decode unit, the execution unit operable, in response to the decode of the instruction, to store a result packed data in a destination storage location that is to be indicated by the instruction, the result packed data to include three new messages for three new rounds but no more than the three new messages for the three new rounds, the three new messages to include a Wj message to be input to a round j of the compression function of the SM3 hash function, and the result packed data to include the message Wj−16.