Data element rearrangement, processors, methods, systems, and instructions
AssigneeIntel Corporation
InventorsChristopher J. Hughes, Jong Soo Park
Life of this patent
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AssigneeIntel Corporation
InventorsChristopher J. Hughes, Jong Soo Park
Estimating the term…
A processor includes a decode unit to decode an instruction indicating a source packed data operand having source data elements and indicating a destination storage location. Each of the source data elements has a source data element value and a source data element position. An execution unit, in response to the instruction, stores a result packed data operand having result data elements each having a result data element value and a result data element position. Each result data element value is one of: (1) equal to a source data element position of a source data element, closest to one end of the source operand, having a source data element value equal to the result data element position of the result data element; and (2) a replacement value, when no source data element has a source data element value equal to the result data element position of the result data element.
A processor comprising:
A method in a processor comprising:
A computer system comprising:
An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing a data element rearrangement instruction, the data element rearrangement instruction to indicate a source packed data operand that is to have a plurality of source data elements that each are to have a plurality of bits and to indicate a destination packed data register, each of the source data elements to have a source data element value and a source data element position relative to a least significant end of the source packed data operand, and the data element rearrangement instruction if executed by a machine is to cause the machine to perform operations comprising to:
Dependencies are inferred from the claim text.