Self-timed random number generator
AssigneeCryptography Research, Inc.
InventorScott C. Best
Life of this patent
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Abstract
The embodiments described herein describe technologies of self-timed pattern generators. The self-timed pattern generators can be used to form a random number generator to generate a random digital value. Asynchronous digital logic in a first generator asynchronously updates a next state based on a current state, a second state of a second generator that is before the first generator in the chain or ring topology, and a third state of a third generator that is after the first generator in the chain or ring topology. The self-timed pattern generators are to output a random digital value based at least in part on the current state output from the first generator.
Claims20
A random number generator comprising:
- a plurality of self-timed pattern generators organized in a chain or ring topology, each comprising an internal latch storing a correcsponding state, wherein asynchronous digital logic in a first generator of the plurality of self-timed pattern generators comprises a first input, a second input, and a third input, wherein the asynchronous digital logic is to asynchronously update and latch a next state based on, at the first input, a current state stored in the internal latch of the first generator, at the second input, a second state stored in the internal latch of a second generator of the plurality of self-timed pattern generators that is before the first generator in the chain or ring topology, and at the third input, a third state stored in the internal latch of a third generator of the plurality of self-timed pattern generators that is after the first generator in the chain or ring topology, and wherein the plurality of self-timed pattern generators is to output a random digital value based at least in part on the current state output from the first generator.
A circuit comprising:
- a first self-timed pattern generator;
- a second self-timed pattern generator;
- and
- a third self-timed pattern generator coupled to the first self-time pattern generator and the second self-timed pattern generator,
- wherein each self-timed pattern generator comprisies an internal latch storing a corresponding state, wherein the third self-timed pattern generator comprises asynchronous digital logic comprising a first input, a second input, and a third input, wherein the asynchronous digital logic is to asynchronously update and latch a next state based on a current state stored in the internal latch of the third self-timed pattern generator at the first input, a second state stored in the internal latch of the first self-timed pattern generator at the second input, and a third state stored in the internal latch of the second self-timed pattern generator at the third input, and wherein an output of the circuit is a random digital value based at least in part on the current state output from the first self-timed pattern generator.
Dependencies are inferred from the claim text.