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US 10,503,474 B2Granted
Methods and instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition
AssigneeTexas Instruments Incorporated
InventorsSrinivas Lingam, Seok-Jun Lee, Manish Goel
Life of this patent
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Abstract
Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.
Claims20
A method of performing a multiplication of a first signed 32-bit operand and a second signed 32-bit operand using 32-bit architecture, the method comprising:
- performing, by a 16-bit multiplier, a signed multiplication of the first 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a first 32-bit product;
- performing, by the 16-bit multiplier, an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand, to generate a second 32-bit product;
- adding, by an adder, the first 32-bit product to the second 32-bit product, to generate a first 32-bit sum;
- performing, by the 16-bit multiplier, an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a third 32-bit product;
- shifting the third 32-bit product right 16 bits and filling the first 16 bit positions with zeroes, to generate a shifted third 32-bit product;
- adding, by the adder, the shifted third 32-bit product and the first 32-bit sum, to generate a second 32-bit sum;
- performing, by the 16-bit multiplier, a signed multiplication of the first 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand, to generate a fourth 32-bit product;
- shifting the second 32-bit sum right 15 bits and filling the first 15 bit positions with a value of the second 32-bit sum, to generate a shifted second 32-bit sum;
- and
- adding the shifted second 32-bit sum and the fourth 32-bit product, to generate a product of the first and second signed 32-bit operands.
7 more elements
A processor to multiply a first signed 32-bit operand by a second signed 32-bit operand, the processor comprising:
- a load store unit to load the first signed 32-bit operand and to load the second signed 32-bit operand;
- a butterfly/adder;
- a 16-bit multiplier;
- a program controller;
- and
- a memory coupled to the program controller, the memory storing instructions;
- wherein, in response to at least one instruction of the instructions, the 16-bit multiplier is configured to:
- perform a signed multiplication of the first 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a first 32-bit product;
- and
- perform a signed multiplication of the last 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand, to generate a second 32-bit product;
- wherein the butterfly/adder is configured to add the first 32-bit product to the second 32-bit product, to generate a first 32-bit sum;
- wherein the 16-bit multiplier is configured to perform an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a third 32-bit product;
- wherein the program controller is configured to execute a first single instruction of the instructions, that comprises respective opcode fields for the load store unit, the butterfly/adder, and the 16-bit multiplier;
- and
- wherein the butterfly/adder opcode field controls the butterfly/adder to shift the third 32-bit product right by a fixed number of bits, wherein the fixed number of bits is 16 bits;
- and
- fill the first 16 bit positions with zeroes, to generate a shifted third 32-bit product, wherein the first single instruction is a shift-right add signed/signed instruction or a shift-right add signed/unsigned instruction.
14 more elements
A processor to multiply a first signed 32-bit operand by a second signed 32-bit operand, the processor comprising:
- local twiddle read only memory (ROM) storing constants for computation;
- and
- an application specific integrated processor (ASIP) core, comprising:
- a load store unit to load the first signed 32-bit operand and to load the second signed 32-bit operand;
- a butterfly/adder;
- a 16-bit multiplier;
- an address register;
- a step register;
- and
- a program controller;
- and
- a memory coupled to the program controller, the memory storing instructions;
- wherein the 16-bit multiplier is configured to:
- perform a signed multiplication of the first 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a first 32-bit product;
- and
- perform a signed multiplication of the last 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand, to generate a second 32-bit product;
- wherein the butterfly/adder is configured to add the first 32-bit product to the second 32-bit product, to generate a first 32-bit sum;
- and
- wherein the 16-bit multiplier is configured to performing an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a third 32-bit product;
- and
- wherein the program controller is configured to execute a first single instruction of the instructions, that:
- shifts the third 32-bit product right by a fixed number of bits, wherein the fixed number of bits is 16 bits;
- and
- fills the first 16 bit positions with zeroes, to generate a shifted third 32-bit product.
21 more elements
A processor to multiply a first signed 32-bit operand by a second signed 32-bit operand, the processor comprising:
- local twiddle read only memory (ROM) storing constants for computation;
- and
- an application specific integrated processor (ASIP) core comprising:
- a load store unit to load the first signed 32-bit operand and to load the second signed 32-bit operand;
- a butterfly/adder;
- a 16-bit multiplier;
- and
- a program controller;
- a block coupled to the ASIP core, the block, comprising:
- core ROM;
- a single port static random access memory (SRAM);
- an arbiter;
- and
- a cyclic redundancy check (CRC) and discrete Fourier transform (DFT);
- and
- a memory coupled to the program controller, the memory storing instructions;
- wherein the 16-bit multiplier is configured to:
- perform a signed multiplication of the first 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a first 32-bit product;
- and
- perform a signed multiplication of the last 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand, to generate a second 32-bit product;
- wherein the butterfly/adder is configured to add the first 32-bit product to the second 32-bit product, to generate a first 32-bit sum;
- wherein the 16-bit multiplier is configured to performing an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a third 32-bit product;
- and
- wherein the program controller is configured to execute a first single instruction of the instructions, that:
- shifts the third 32-bit product right by a fixed number of bits, wherein the fixed number of bits is 16 bits;
- and
- fills the first 16 bit positions with zeroes, to generate a shifted third 32-bit product.
24 more elements
A processor to multiply a first signed 32-bit operand by a second signed 32-bit operand, the processor comprising:
- local twiddle read only memory (ROM) storing constants for computation;
- and
- an application specific integrated processor (ASIP) core comprising:
- a load store unit to load the first signed 32-bit operand and to load the second signed 32-bit operand;
- a butterfly/adder;
- a 16-bit multiplier;
- and
- a program controller;
- command registers coupled to the ASIP core;
- command and switch control coupled to the command registers;
- a co-processor slave interface coupled to the command and switch control, the co-processor slave interface coupled to a central processing unit (CPU);
- and
- a memory coupled to the program controller, the memory storing instructions;
- wherein the 16-bit multiplier is configured to:
- perform a signed multiplication of the first 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a first 32-bit product;
- and
- perform a signed multiplication of the last 16 bits of the first signed 32-bit operand and the first 16 bits of the second signed 32-bit operand, to generate a second 32-bit product;
- wherein the butterfly/adder is configured to add the first 32-bit product to the second 32-bit product, to generate a first 32-bit sum;
- wherein the 16-bit multiplier is configured to performing an unsigned multiplication of the last 16 bits of the first signed 32-bit operand and the last 16 bits of the second signed 32-bit operand, to generate a third 32-bit product;
- and
- wherein the program controller is configured to execute a first single instruction of the instructions, that:
- shifts the third 32-bit product right by a fixed number of bits, wherein the fixed number of bits is 16 bits;
- and
- fills the first 16 bit positions with zeroes, to generate a shifted third 32-bit product.
21 more elements
Dependencies are inferred from the claim text.