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US 10,503,471 B2Granted
Electronic devices and operation methods of the same
AssigneeSamsung Electronics Co., Ltd.
InventorDonguk Moon
Life of this patent
Estimating the term…
Abstract
An electronic device according to some example embodiments includes a clock management circuit configured to control a clock signal and a processor circuit directly connected to the clock management circuit and configured to provide a clock control request for the clock signal to the clock management circuit according to an operation status of the processor circuit.
Claims22
An electronic device comprising:
- a clock management circuit configured to control a clock signal;
- and
- a processor circuit directly connected to the clock management circuit, the processor circuit configured to communicate a clock control request associated with the clock signal to the clock management circuit according to an operation status of the processor circuit,
- wherein the clock control request includes a clock disable request and a clock enable request, and
- wherein the clock management circuit is further configured to,
- even when the clock disable request is received at the clock management circuit, maintain an enabled status of a clock signal input to the processor circuit without disabling the clock signal, based on a determination that a time interval between reception of the clock disable request at the clock management circuit and immediately preceding enabling of the clock signal is less than or equal to a particular threshold time.
3 more elements
An operation method of an electronic device, the operation method comprising:
- determining an operation status of a processor circuit of the electronic device;
- and
- directly communicating, based on using the processor circuit, a clock control request associated with a clock signal to a clock management circuit configured to control the clock signal according to the operation status of the processor circuit
- wherein the clock control request includes a clock disable request and a clock enable request, and
- wherein the clock management circuit is further configured to:
- even when the clock disable request is received at the clock management circuit, maintain an enabled status of a clock signal input to the processor circuit without disabling the clock signal, based on a determination that a time interval between reception of the clock disable request at the clock management circuit and immediately preceding enabling of the clock signal is less than or equal to a particular threshold time.
3 more elements
An electronic device comprising:
- a first processor circuit and a second processor circuit configured to support hardware cache coherence;
- and
- a clock management circuit configured to control both a clock signal of the first processor circuit and a clock signal of the second processor circuit,
- wherein the second processor circuit is configured to communicate a clock enable request to the clock management circuit based on a determination that the second processor circuit has received a cache coherence signal from the first processor circuit, and
- the clock management circuit is configured to enable the second processor circuit in response to the clock enable request.
2 more elements
Dependencies are inferred from the claim text.