Memory device and operating method including a partial program operation and a partial erase operation thereof

A method of operating a memory device including a plurality of memory cells coupled between a source line and a bit line, the method comprising:

• performing a first program operation on memory cells relatively closer to the bit lines and memory cells relatively closer to the source line, respectively, among the plurality of memory cells;
• performing a first erase operation on memory cells, among the plurality of memory cells, except the memory cells on which the first program operation is performed;
• performing a second program operation on memory cells among the memory cells on which the first erase operation is performed;
• performing a second erase operation on memory cells, among the plurality of memory cells, except the memory cells on which the first program operation or the second program operation are performed;
• and
• performing a third program operation on memory cells among the memory cells on which the second erase operation is performed.

A method of operating a memory device including a plurality of pages coupled between a source line and a bit line, the method comprising:

• programming an Nth page relatively close to the source line and an Nth page relatively close to the bit line, respectively, among the plurality of pages;
• erasing pages between the Nth pages;
• and
• programming the pages erased between the Nth pages,
• wherein N is a positive integer.