Providing extended dynamic random access memory (DRAM) burst lengths in processor-based systems

A processor-based system for providing extended dynamic random access memory (DRAM) burst lengths, comprising:

• a DRAM circuit configured to provide 4-bit-wide data access and a 128-bit internal data prefetch;
• and
• a memory controller communicatively coupled to the DRAM circuit;
• the DRAM circuit configured to provide an extended DRAM burst length of 32 bits by being configured to:
• receive, from the memory controller, a memory read request;
• perform an internal prefetch of 128 bits of data;
• generate an error correction code (ECC) over all of the 128 bits of data;
• and
• return all of the 128 bits of data to the memory controller, responsive to the memory read request:
• wherein:
• the DRAM circuit is further configured to:
• receive, from the memory controller, a memory write request comprising 128 bits of write data;
• generate an ECC over the 128 bits of write data;
• and
• write the 128 bits of write data responsive to the memory write request, without performing a read/modify/write (RMW) operation;
• the memory write request comprises a burst length selection indicator;
• the DRAM circuit is configured to provide the extended DRAM burst length of 32 bits responsive to detecting that the burst length selection indicator of the memory write request is in a set state;
• and
• the burst length selection indicator comprises a burst chop (BC) indicator of the memory write request that is repurposed as the burst length selection indicator.

A method for providing extended dynamic random access memory (DRAM) burst lengths, comprising:

• receiving, by a DRAM circuit configured to provide 4-bit-wide data access and a 128-bit internal data prefetch, a memory read request from a memory controller;
• performing an internal prefetch of 128 bits of data;
• generating an error correction code (ECC) over all of the 128 bits of data;
• and
• returning, by the DRAM circuit, all of the 128 bits of data to the memory controller, responsive to the memory read request;
• wherein:
• the memory read request comprises a burst length selection indicator;
• returning, by the DRAM circuit, all of the 128 bits of data to the memory controller is further responsive to detecting that the burst length selection indicator of the memory read request is in a set state;
• and
• the burst length selection indicator comprises a burst chop (BC) indicator of the memory read request that is repurposed as the burst length selection indicator.