Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration

A method of fabricating a stacked wafer processor-memory system, the method comprising:

• fabricating a plurality of specialized processor wafers, each of the specialized processor wafers comprising a memory area and a multitude of specialized processors embedded in the memory area of the each specialized processor wafer, each of the specialized processors being configured to perform a specified set of operations using an associated memory domain of the memory area of the each specialized processor wafer;
• connecting a plurality of subordinate general management processors to the specialized processors, each of the subordinate general management processors being configured to manage an associated set of the specialized processors;
• connecting a lead general management processor to an input/output connection and to the subordinate general management processors to communicate therewith;
• connecting each of the subordinate general management processor to a protocol converter chip to allow the specialized processors to communicate with the subordinate general management processors;
• and
• forming a network of inter-strata through silicon vias for delivering power and ground to the specialized processor wafers.

A stacked-wafer processor-memory system comprising:

• a plurality of wafers arranged in a stack, including
• at least one memory wafer comprising a multitude of memory domains, and
• at least one processor wafer comprising a multitude of specialized processors, each of the specialized processors controlling a respective one of the memory domains of the memory wafer;
• an input/output connection;
• a multitude of general management processors including
• a multitude of subordinate general management processors, each of the subordinate general management processors being connected to a respective one, associated set of the specialized processors for controlling said associated set of the specialized processors, and
• a lead general management processor in communication with the input/output connection and with the subordinate general management processors for transmitting data to and receiving data from the subordinate general management processors;
• a plurality of protocol converter chips, wherein each of the subordinate general management processors is connected to one of the protocol converter chips to allow the specialized processors to communicate with the subordinate general management processors;
• and
• a network of through silicon vias for delivering power and ground to the specialized processor wafers and for communicating with the general management processors.