Electronic device and power management method

A power management method executed by an electronic device which is connectable with a host via a serial interface,

• the electronic device including
• a link configured with a plurality of lanes, each of which includes a differential signal wire pair for transmission and a differential signal wire pair for reception,
• a plurality of transmitter circuits that respectively correspond to the plurality of lanes, and is configured to transmit data via the differential signal wire pair for transmission of each of the corresponding lanes,
• a plurality of receiver circuits that respectively correspond to the plurality of lanes, and is configured to receive data via the differential signal wire pair for reception of each of the corresponding lanes, and
• a control circuit,
• the method comprising:
• causing a state of the electronic device to transition from a normal operation state in which the plurality of transmitter circuits and the plurality of receiver circuits are in an active state, to a first low-power state in which the plurality of transmitter circuits are maintained in an active state and the plurality of receiver circuits are in an inactive state except for one of the receiver circuits corresponding to one lane among the plurality of lanes;
• and
• causing the state of the electronic device to transition from the first low-power state to the normal operation state in a case where reception of specific information is detected on the one lane.

A storage device which is connectable with a host via a serial interface including a link configured with a plurality of lanes, each of which includes a differential signal wire pair for transmission and a differential signal wire pair for reception, the device comprising:

• a nonvolatile memory;
• a controller for the nonvolatile memory;
• and
• a host interface circuit including
• a plurality of transmitter circuits that respectively correspond to the plurality of lanes, and is configured to transmit data via the differential signal wire pair for transmission of each of the corresponding lanes,
• a plurality of receiver circuits that respectively correspond to the plurality of lanes, and is configured to receive data via the differential signal wire pair for reception of each of the corresponding lanes, and
• a control circuit configured to allow a state of the storage device to transition from a normal operation state in which the plurality of transmitter circuits and the plurality of receiver circuits are in an active state, to a first low-power state in which the plurality of transmitter circuits are maintained in an active state and the plurality of receiver circuits are in an inactive state except for one of the receiver circuits corresponding to one lane among the plurality of lanes.