Thread importance based processor core parking and frequency selection

A computing device comprising:

• a processor core;
• storage hardware storing associations of different frequency ranges with different importance levels for threads, where the different frequency ranges are determined based on efficiencies of the processor core at each of respective different frequencies at which the processor core can run, each efficiency corresponding to a respective ratio between frequency and power consumption;
• a thread importance determination module configured to determine an importance level of a first thread scheduled to run on the processor core, the importance level being one of multiple different importance levels that threads running on the processor core can have;
• and
• a core frequency configuration module configured to
• select a frequency range associated with the importance level from among the different frequency ranges, wherein each frequency range comprises corresponding upper and lower frequencies within which the processor core is allowed to run to execute a thread;
• and to
• configure the processor core to run at the frequency range while running the first thread;
• wherein the importance levels include a first importance level and a second importance level that is lower than the first importance level, and wherein the frequency ranges are determined based on the efficiencies such that operation of the processor core in a frequency range associated with the second importance level is more efficient than operation of the processor core in a frequency range associated with the first importance level.

Computer-readable storage media storing information configured to cause a computing device to perform a process, the process comprising:

• executing a workload of a processor core at each of respective different frequencies among frequencies at which the processor core can run;
• programmatically determining, based on the executing, efficiencies of the processor core at each of the respective different frequencies, each efficiency corresponding to a respective ratio between frequency and power consumption;
• determining frequency ranges based on the determined efficiencies, and associating the frequency ranges with importance levels, respectively, wherein each frequency range comprises corresponding upper and lower frequencies within which the processor core is allowed to run to execute a thread;
• determining an importance level of a first thread scheduled to run on the processor core, the importance level being one of the importance levels;
• selecting, from among the determined frequency ranges, a frequency range associated with the determined importance level;
• configuring the processor core to run at the selected frequency range while running the first thread;
• and
• wherein the importance levels include a first importance level and a second importance level that is lower than the first importance level, and wherein determining the frequency ranges based on the determined efficiencies is such that operation of the processor core in a frequency range associated with the second importance level is more efficient than operation of the processor core in a frequency range associated with the first importance level.