Low-power multi-phase clock distribution on silicon
AssigneeAdvanced Micro Devices, Inc.
InventorDirk J. Robinson
Life of this patent
Estimating the term…
Abstract
Various semiconductor chip clock signal pathways are disclosed. In one aspect, a semiconductor chip with a receiver includes a clock signals pathway for conveying plural clock phases in the receiver. The clock signals pathway includes plural wires in an arrangement that has a first edge, a second edge separated from the first edge and a midline between the first edge and the second edge. Each of the wires conveys a clock phase. The wires of the arrangement are routed so that, along a length of the clock signals pathway, each of the wires spends about the same percentage of time at or nearer the first edge or the second edge and at or nearer the midline.
Claims20
A semiconductor chip having a receiver, comprising:
- a clock signals pathway for conveying plural clock phases in the receiver, the clock signals pathway including plural wires in an arrangement having a first edge, a second edge separated from the first edge and a midline between the first edge and the second edge, each of the wires conveying a clock phase;
- and
- the wires of the arrangement being routed so that, along a length of the clock signals pathway, each of the wires spends about the same percentage of time at or nearer the first edge or the second edge and at or nearer the midline.
A semiconductor chip having a receiver, comprising:
- a clock signals pathway for conveying plural clock phases and plural dummy clock phases in the receiver, the clock signals pathway including plural wires in an arrangement having a first side and a second side, each of the wires conveying a clock phase or a dummy clock phase;
- a first group of the wires carrying the plural clock phases in order;
- a second group of the wires carrying the plural dummy clock phases, the second group of wires bracketing the first group of wires;
- and
- first and second ground wires bracketing the plural wires.
A method of manufacturing a semiconductor chip having a receiver, comprising:
- fabricating a clock signals pathway for conveying plural clock phases in the receiver, the clock signals pathway including plural wires in an arrangement having a first edge, a second edge separated from the first edge and a midline between the first edge and the second edge, each of the wires conveying a clock phase;
- and
- routing the wires of the arrangement so that, along a length of the clock signals pathway, each of the wires spends about the same percentage of time at or nearer the first edge or the second edge and at or nearer the midline.
A method of manufacturing a semiconductor chip having a receiver, comprising:
- fabricating a clock signals pathway for conveying plural clock phases and plural dummy clock phases in the receiver, the clock signals pathway including plural wires in an arrangement having a first side and a second side, each of the wires conveying a clock phase or a dummy clock phase;
- a first group of the wires carrying the plural clock phases in order;
- a second group of the wires carrying the plural dummy clock phases, the second group of wires bracketing the first group of wires;
- and
- fabricating first and second ground wires bracketing the plural wires.
Dependencies are inferred from the claim text.