Synthesis for random testability using unreachable states in integrated circuits

A computer-implemented method of using unreachable states as don't care conditions to change logic of an integrated circuit design, said method comprising:

• determining, using a hardware processor, from an existing logic circuit design, unreachable states;
• computing, using the hardware processor, “don't care” values in terms of said unreachable states;
• propagating, using the hardware processor, said don't care values to a circuit having a local logic gate in a region of said existing logic circuit design having outputs of limited controllability;
• and
• modifying, using the hardware processor, said circuit having said local gate to increase its random testability by one of:
• adding don't care values if said local gate exhibits limited 0-controllability, or subtracting don't care values if said local gate exhibits limited 1-controllability.

A system of testing an integrated circuit having a random resistant logic circuit that exhibits limited controllability of random resistant output signals in a functional mode of operation, said system comprising:

• a control-improving logic circuit operatively connected to said random resistant logic circuit;
• said control-improving logic circuit configured to receive input net signals corresponding to unreachable states of said random resistant logic circuit during said functional mode of operation;
• and
• said control-improving logic circuit configured for automatic activation responsive to said input net signals in a testing mode of operation to increase controllability of said random resistant output signals, said activated control-improving logic circuit preserving original functionality of said output signals of said random resistant logic circuit responsive to said input net signals in the functional mode, and yielding new output signals of said combinational logic circuit corresponding to said unreachable states for testing said random resistant logic circuit in said testing mode of operation, said unreachable states being a state of said integrated circuit that can be accessed only during the testing mode of said integrated circuit and is not reachable when said integrated circuit is operating in the functional mode.