Multi-rate high-speed bus with statistical aggregator

A device, comprising:

• a bus interface to transmit outgoing information and receive incoming information via a bus;
• a buffer coupled to the bus interface;
• a traffic estimator coupled to the bus interface, the traffic estimator to analyze present traffic and to estimate future traffic based on the analysis of the present traffic;
• a traffic detector coupled to the traffic estimator, the traffic detector to make a determination of whether the bus interface is to transmit traffic via the bus at a first traffic rate or at a second traffic rate, wherein the first traffic rate and the second traffic rate are different traffic rates and wherein the determination is at least partially based on the traffic estimator's estimate of the future traffic;
• and
• control logic to cause the bus interface to transmit traffic via the bus at the first traffic rate and to direct traffic to be transmitted at the second traffic rate to the buffer in response to the traffic detector's making a determination of whether the bus interface is to transmit traffic via the bus at the first traffic rate.