US 10,484,218 B2 · PWM demodulation

Abstract

A receiver for demodulating a pulse width modulated (“PWM”) signal, comprises: a voltage level shifter for shifting the PWM signal to predefined transistor voltage levels; a half-rate PWM decoder for receiving the shifted PWM signal; and a 2-bit-to-N-bit deserializer. The half-rate PWM decoder comprises a first decoder core, a second decoder core, a controller, and a sampler and retiming circuit. The first decoder core and the second decoder core are configured to decode alternating periods of the shifted PWM signal. The controller is coupled to the first decoder core, the second decoder core, the sampler and retiming circuit. The retiming circuit is configured to receive clock signals from the controller and to output half-rate even data from the first decoder core and half-rate odd data from the second decoder core. Outputs of the retiming circuit and an output of the controller are coupled to inputs of the deserializer.

Claims20

Dependent claims

A receiver for demodulating a pulse width modulated (“PWM”) signal,

comprising:
a voltage level shifter for shifting the PWM signal to predefined transistor voltage levels;
a half-rate PWM decoder for receiving the shifted PWM signal, wherein the half-rate PWM decoder comprises a first decoder core, a second decoder core, a controller, and a sampler and retiming circuit, wherein the first decoder core and the second decoder core are configured to decode alternating periods of the shifted PWM signal;
and
a 2-bit-to-N-bit deserializer,
wherein the controller is coupled to the first decoder core, the second decoder core, the sampler and retiming circuit,
wherein the retiming circuit is configured to receive clock signals from the controller and to output half-rate even data from the first decoder core and half-rate odd data from the second decoder core, and
wherein outputs of the retiming circuit for the half-rate even data and for the half-rate odd data and an output of the controller for a half-rate clock signal are coupled to inputs of the deserializer for parallel output of N bits.

5 more elements

A method for demodulating a pulse width modulated (“PWM”) signal comprising the steps of:

shifting voltage levels of the PWM signal to predefined transistor voltage levels;
decoding the PWM signal using half-rate decoder cores into half-rate even data and half-rate odd data, wherein the half-rate decoder cores decode alternating periods of the shifted PWM signal;
sampling and retiming of the decoded half-rate even data and the decoded half-rate odd data for parallel output;
outputting the sampled half-rate even data and the sampled half-rate odd data in parallel using a half-rate clock signal;
and
converting the outputted half-rate even data and the outputted half-rate odd data for parallel output by a 2-bit-to-N-bit deserializer.

3 more elements

Dependencies are inferred from the claim text.

PWM demodulation

Life of this patent

PWM demodulation

Life of this patent

Abstract

Claims20