Receiver

A receiver comprising:

• an A/D converter that performs an analog digital conversion to an input signal;
• an equalizer that equalizes an output of the A/D converter, eliminates an inter-code interference and obtains a data output;
• a timing recovery part that generates a recovery clock by using the data output of the equalizer;
• a detector that detects a timing when the input signal varies from a non-signal state and has reached a predetermined threshold;
• and
• an initial phase setting part that sets as an initial phase of the recovery clock from the timing recovery part, a timing when a predetermined time has elapsed after the timing detected by the detector, wherein:
• the timing recovery part includes a phase lock loop that outputs a reference clock and a divider that divides the reference clock of the phase lock loop;
• and
• when the recovery clock is generated, the phase lock loop outputs the reference clock, with the initial phase of the recovery clock set by the initial phase setting part as a start, the divider starts to divide the frequency of the reference clock, generates dual-phase clocks and generates the recovery clock corresponding to the dual-phase clocks, and wherein
• the detector includes a comparator arranged in parallel with the A/D converter;
• the detector detects the timing that has reached the threshold by the comparator and obtains a output signal;
• and
• the initial phase setting part includes a delay circuit that delays outputs the output signal to the timing recovery part with a delay of the output signal of the comparator for a predetermined time, and obtains the initial phase of the recovery clock.