Clock and data recovery for pulse based multi-wire link
AssigneeQUALCOMM Incorporated
InventorShoichiro Sengoku
Life of this patent
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Abstract
A method and an apparatus are provided. The apparatus may include a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.
Claims10
A clock recovery circuit, comprising:
- a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals;
- combinational logic configured to provide a second pulse in response to the first pulse;
- a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse;
- and
- a plurality of output flip-flops configured to capture the first state when triggered by the third pulse,
- wherein the first state identifies which of the plurality of input signals has received input pulses.
Dependencies are inferred from the claim text.