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US 10,484,027 B2Granted
Glitch free phase selection multiplexer enabling fractional feedback ratios in phase locked loops
AssigneeQUALCOMM Incorporated
InventorsDebesh Bhatta, Deping Huang, Jeffrey Mark Hinrichs
Life of this patent
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Abstract
In some aspects, a method for phase multiplexing includes receiving a plurality of phases, selecting one of the plurality of phases based on a select signal using a multiplexer, and outputting the selected one of the plurality of phases at an output of the multiplexer. The method also includes gating the output of the multiplexer during a glitch at the output of the multiplexer.
Claims30
A phase selection multiplexer, comprising:
- a multiplexer configured to receive a plurality of phases, to select one of the plurality of phases based on a select signal, and to output the selected one of the plurality of phases at an output of the multiplexer;
- a flip-flop having a clock input, a data input, and an output, wherein the clock input of the flip-flop is coupled to the output of the multiplexer;
- and
- a gate circuit coupled to the data input of the flip-flop, and also configured to receive the output of the flip-flop and an early output signal generated using another multiplexer, wherein the gate circuit is configured to generate a gate signal based on the output of the flip-flop and the early output signal, and to output the gate signal to the data input of the flip-flop, wherein the gate signal causes the flip-flop to gate the output of the multiplexer during a glitch at the output of the multiplexer.
1 more element
A phase selection multiplexer comprising:
- a first multiplexer configured to receive a plurality of phases, to select a first one of the plurality of phases based on a first select signal, and to output the selected first one of the plurality of phases at an output of the first multiplexer;
- a first flip-flop having a clock input, a data input coupled to a first gate signal, and a first output, wherein the clock input of the first flip-flop is coupled to the output of the first multiplexer;
- a second multiplexer configured to receive the plurality of phases, to select a second one of the plurality of phases based on a second select signal, and to output the selected second one of the plurality of phases at an output of the second multiplexer;
- a second flip-flop having a clock input coupled to the output of the second multiplexer, a data input coupled to a second gate signal, and an output;
- and
- a gate circuit coupled to the output of the first flip-flop and the output of the second flip-flop, wherein the gate circuit is configured to generate the first gate signal, and to output the first gate signal to the data input of the first flip-flop, wherein the gate circuit is configured to generate the first gate signal based on the output of the first flip-flop and the output of the second flip-flop.
3 more elements
A method for phase multiplexing, comprising:
- receiving a plurality of phases;
- selecting one of the plurality of phases based on a select signal using a multiplexer;
- outputting the selected one of the plurality of phases at an output of the multiplexer to a flip-flop;
- and
- gating the output of the multiplexer using the flip-flop and a gating circuit configured to receive the output of the flip-flop and an early output signal generated using another multiplexer and generate a gating signal based on the output of the flip-flop and the early output signal, the gating signal causing the flip-flop to gate the output of the multiplexer during a glitch at the output of the multiplexer.
2 more elements
A method for phase multiplexing comprising:
- receiving a plurality of phases;
- selecting one of the plurality of phases based on a first select signal using a first multiplexer;
- outputting the selected one of the plurality of phases at an output of the first multiplexer to a first flip-flop;
- selecting a second one of the plurality of phases based on a second select signal using a second multiplexer;
- outputting the selected second one of the plurality of phases at an output of the second multiplexer to a second flip-flop;
- and
- gating the output of the first multiplexer using the first flip-flop and a gating circuit causing the first flip-flop to gate the output of the first multiplexer during a glitch at the output of the first multiplexer using a gating signal based on an output of the first flip-flop and an output of the second flip-flop.
4 more elements
An apparatus for phase multiplexing, comprising:
- means for receiving a plurality of phases;
- means for selecting one of the plurality of phases based on a select signal;
- means for outputting the selected one of the plurality of phases at an output;
- and
- means for gating the output during a glitch at the output, the means for gating including a flip-flop and a gating circuit causing the flip-flop to gate the output, wherein the gating circuit is configured to receive the output of the flip-flop and an early output signal generated using another multiplexer and to generate a gating signal based on the output of the flip-flop and the early output signal.
2 more elements
An apparatus for phase multiplexing comprising:
- means for receiving a plurality of phases;
- means for selecting a first one of the plurality of phases based on a first select signal;
- means for outputting the selected first one of the plurality of phases at a first output, the means for outputting the first one of the plurality of phases including a first flip-flop;
- means for selecting a second one of the plurality of phases based on a second select signal;
- means for outputting the selected second one of the plurality of phases at a second output, the means for outputting the second one of the plurality of phases including a second flip-flop;
- and
- means for gating the first output during a glitch, the means for gating including a gating circuit receiving the first output and the second output and causing the first flip-flop to gate the means for selecting the first one of the plurality of phases based on the first output and the second output.
4 more elements
Dependencies are inferred from the claim text.