US 10,484,021 B1 · Log-likelihood ratio processing for linear block code decoding

Abstract

Apparatuses and methods relating generally to a decoder. In an apparatus, a control circuit receives first-third sign signals, a partial sum signal, a function select signal, and a carry signal as an input vector to provide an output sign and a vector select. A select generation circuit receives the first and second sign signals and the partial sum signal to provide an add/subtract select signal. A subtractor subtracts from a first absolute value signal a second absolute value signal to provide the third sign signal and a difference signal. Responsive to the add/subtract select signal, an adder/subtractor either adds or subtracts the first absolute value signal to or from the second absolute value signal to provide the carry signal and a sum/difference signal. A multiplexer selects from the first and second absolute value signals, the difference signal, and the sum/difference signal a selected value signal responsive to the vector select.

Claims13

Dependent claims

A decoder, comprising:

a control circuit configured to receive a first sign signal, a second sign signal, a partial sum signal, a function select signal, a third sign signal, and a carry signal as an input vector to provide an output sign signal and a vector select signal;
a select generation circuit configured to receive the first sign signal, the second sign signal, and the partial sum signal to provide an add/subtract select signal;
a subtractor configured to subtract from a first absolute value signal a second absolute value signal to provide the third sign signal and a difference signal;
responsive to the add/subtract select signal, an adder/subtractor configured to either add or subtract the first absolute value signal to or from the second absolute value signal to provide the carry signal and a sum/difference signal;
and
a multiplexer configured to select from the first absolute value signal, the second absolute value signal, the difference signal, and the sum/difference signal a selected value signal responsive to the vector select signal.

3 more elements

A method for decoding, comprising:

receiving by a decoder a first sign signal, a second sign signal, a partial sum signal, a function select signal, a third sign signal, and a carry signal as an input vector to a control circuit thereof and a first absolute value signal and a second absolute value signal;
looking up in a lookup table circuit of the control circuit an output sign signal and a vector select signal in response to the input vector;
generating by a select generation circuit an add/subtract select signal in response to the first sign signal, the second sign signal, and the partial sum signal;
subtracting from the first absolute value signal the second absolute value signal by a subtractor to provide the third sign signal and a difference signal;
responsive to the add/subtract select signal, selectively either adding to or subtracting from the first absolute value signal the second absolute value signal by an adder/subtractor to provide the carry signal and a sum/difference signal;
and
selecting with a multiplexer from the first absolute value signal, the second absolute value signal, the difference signal, and the sum/difference signal a selected value signal responsive to the vector select signal.

4 more elements

Dependencies are inferred from the claim text.

Log-likelihood ratio processing for linear block code decoding

Life of this patent

Log-likelihood ratio processing for linear block code decoding

Life of this patent

Abstract

Claims13