Controller, semiconductor memory system and operating method thereof

A memory system comprising:

• a controller suitable for receiving a message from a host;
• and
• a memory device suitable for storing an encoded message;
• wherein the controller includes:
• an error correction code (ECC) circuit suitable for generating a square message matrix of k×k by using the message, minimizing a length of each codes included in the square message matrix, and generating the encoded message by encoding the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code;
• and
• a processor suitable for providing the encoded message to the memory device and obtaining the encoded message in the memory device for decoding,
• wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix,
• wherein the upper triangular matrix includes “β” numbers of message blocks, each of which has a size of “α+1”, and “(N−β)” numbers of message blocks, each of which has a size of “α”, and
• wherein the “α”, “β” and “N” have relationships represented by following equations
• α
• =
• ⌊
• M
• N
• ⌋
• β
• =
• M
• ⁢
• ⁢
• mod
• ⁢
• ⁢
• N
• where the “M” represents a size of the message input from the host and the “N” represents a number of message blocks forming the upper triangular matrix,
• wherein the error correction code (ECC) circuit further generates a parity block for each row of the square message matrix, and
• wherein each size of the zero-padding blocks has the same as the parity block.

An operating method of a memory system including a controller and a memory device, the operating method comprising:

• reading from the memory device, by the controller, an encoded message including a square message matrix of k×k;
• generating, by the controller, a decoded message by decoding the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code;
• and
• providing, by the controller, the decoded message to a host,
• wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix,
• wherein the upper triangular matrix includes “β” numbers of message blocks, each of which has a size of “α+1”, and “(N−β)” numbers of message blocks, each of which has a size of “α”, and
• wherein “α”, “β” and N have relationships represented by following equations
• α
• =
• ⌊
• M
• N
• ⌋
• β
• =
• M
• ⁢
• ⁢
• mod
• ⁢
• ⁢
• N
• where “M” represents a size of the encoded message and “N” represents a number of message blocks forming the upper triangular matrix, and
• wherein a length of each codes included in the squared message matrix is minimized and each size of the zero-padding blocks is the same as a parity block for each row of the square message matrix.

A memory system comprising:

• a memory device suitable for storing an encoded message;
• and
• a controller suitable for reading the encoded message, decoding the encoded message and providing a decoded message to a host;
• wherein the controller includes:
• an error correction code (ECC) circuit suitable for reading from the memory device the encoded message including a square message matrix of k×k, and generating the decoded message by decoding the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code;
• and
• a processor suitable for providing the decoded message to the host,
• wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix,
• wherein the upper triangular matrix includes “β” numbers of message blocks, each of which has a size of “α+1”, and “(N−β)” numbers of message blocks, each of which has a size of “α”, and
• wherein the “α”, “β” and “N” have relationships represented by following equations
• α
• =
• ⌊
• M
• N
• ⌋
• β
• =
• M
• ⁢
• ⁢
• mod
• ⁢
• ⁢
• N
• where the “M” represents a size of the encoded message and the “N” represents a number of message blocks forming the upper triangular matrix, and
• wherein a length of each codes included in the squared message matrix is minimized and each size of the zero-padding blocks is the same as a parity block for each row of the square message matrix.