Systems and methods for decoding quasi-cyclic (QC) low-density parity-check (LDPC) codes

A decoder circuit, comprising:

• an input configured to receive an encoded message generated based on a quasi-cyclic low-density parity check (QC-LDPC) code associated with a parity check matrix,
• wherein the parity check matrix is constructed by expanding a plurality of elements of a base matrix using a plurality of submatrices respectively,
• wherein a submatrix of the plurality of submatrices has a circulant weight greater than one;
• a layer process unit configured to process a plurality of layers of the parity check matrix respectively to generate a plurality of log-likelihood ratio (“LLR”) values corresponding to a plurality of variable nodes associated with the encoded message, each layer including a plurality of rows of the parity check matrix,
• wherein the layer process unit configured to process a first layer includes:
• a plurality of row process units configured to process a first plurality of rows of the first layer in parallel to generate a plurality of row update values for the plurality of variable nodes;
• and
• a layer update unit coupled to the plurality of row process units and configured to generate a first LLR value associated with a first variable node using first and second row update values for the first variable node;
• and
• an output configured to provide a decoded message generated based on the plurality of LLR values.