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US 10,484,008 B2Granted
Memory system with on-the-fly error detection and termination and operating method thereof
AssigneeSK hynix Inc.
InventorsFan Zhang, Chenrong Xiong, Abhiram Prabhakar, Aman Bhatia, Yu Cai, Naveen Kumar
Life of this patent
Estimating the term…
Abstract
Decoding method includes calculating cyclic redundancy check (CRC) parity bits for data on-the-fly; performing a low-density parity-check (LDPC) decoding for the data; if it is determined that an iteration of is finished, updating the calculated CRC parity bits to generate CRC parity bits; comparing the generated CRC parity bits with CRC bits included in the data; and terminating the LDPC decoding based on the comparison result.
Claims18
A decoding method, comprising:
- calculating cyclic redundancy check (CRC) parity bits for data on-the-fly while the data is decoded using low-density parity-check (LDPC) decoding, the calculating of CRC parity bits being performed at each of a plurality of iterations of the LDPC decoding before the LDPC decoding is complete;
- updating the calculated CRC parity bits to generate CRC parity bits after each iteration of the LDPC decoding;
- comparing the generated CRC parity bits with CRC bits included in the data to determine whether the generated CRC parity bits match the CRC bits in the data;
- and
- terminating the LDPC decoding when the comparing indicates that the generated CRC parity bits match the CRC bits in the data.
2 more elements
A memory system, comprising:
- a storage;
- and
- a decoder coupled to the storage and suitable for:
- calculating cyclic redundancy check (CRC) parity bits for data from the storage on-the-fly while the data is decoded using low-density parity-check (LDPC) decoding, the calculating of CRC parity bits being performed at each of a plurality of iterations of the LDPC decoding before the LDPC decoding is complete;
- updating the calculated CRC parity bits to generate CRC parity bits after each iteration of the LDPC decoding;
- comparing the generated CRC parity bits with CRC bits included in the data to determine whether the generated CRC parity bits match the CRC bits in the data;
- and
- terminating the LDPC decoding when the comparing indicates that the generated CRC parity bits match the CRC bits in the data.
5 more elements
A memory controller, comprising:
- a receiver suitable for receiving data;
- and
- a decoder coupled with the receiver and suitable for:
- calculating cyclic redundancy check (CRC) parity bits for data on-the-fly while the data is decoded using low-density parity-check (LDPC) decoding, the calculating of CRC parity bits being performed at each of a plurality of iterations of the LDPC decoding before the LDPC decoding is complete;
- updating the calculated CRC parity bits to generate CRC parity bits after each iteration of the LDPC decoding;
- comparing the generated CRC parity bits with CRC bits included in the data to determine whether the generated CRC parity bits match the CRC bits in the data;
- and
- terminating the LDPC decoding when the comparing indicates that the generated CRC parity bits match the CRC bits in the data.
5 more elements
Dependencies are inferred from the claim text.