Back to results
US 10,484,004 B2Granted
Delta-sigma modulator
AssigneeMediatek Inc.
InventorTien-Yu Lo
Life of this patent
Estimating the term…
Abstract
A delta-sigma modulator comprising: a first loop filter for filtering a first signal to a second signal, a second loop filter for filtering a third signal, a comparator, a register coupled to the comparator, a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator, a first path causing a delayed signal to be linearly combined with an input signal to form the first signal, and a second path causing the delayed signal to be linearly combined with the second signal to form the third signal, wherein the delayed signal may be formed by delaying an output signal of the register.
Claims22
A delta-sigma modulator (DSM) comprising:
- a first loop filter for filtering a first signal to a second signal;
- a second loop filter for filtering a third signal;
- a comparator;
- a register coupled to the comparator;
- a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator;
- a first path coupled between the register and the first loop filter, causing a delayed signal to be linearly combined with an input signal to form the first signal;
- and
- a second path coupled between the register and the second loop filter, causing the delayed signal to be linearly combined with the second signal to form the third signal;
- wherein:
- the delayed signal is formed by delaying an output signal of the register;
- and
- during a second phase and a third phase, the first capacitor bank is conducted to the comparator;
- and
- during a fourth phase and a repeated first phase, the second capacitor bank is conducted to the comparator.
11 more elements
A DSM comprising:
- a first sum circuit coupled to an input node, a ninth node and a first node;
- a first loop filter coupled to the first node and a second node;
- a second sum circuit coupled to the second node, the ninth node and a third node;
- a second loop filter coupled to the third node and a fourth node;
- a third sum circuit coupled to the second node, the fourth node and a fifth node;
- a first capacitor bank and a second capacitor bank;
- a first front switch coupled between the fifth node and the first capacitor bank;
- a second front switch coupled between the fifth node and the second capacitor bank;
- a first back switch coupled between the first capacitor bank and a sixth node;
- a second back switch coupled between the second capacitor bank and the sixth node;
- a comparator coupled to the sixth node and a seventh node;
- a register coupled to the seventh node and an output node;
- and
- a delay circuit coupled to the output node and the ninth node.
11 more elements
A DSM comprising:
- a first loop filter for filtering a first signal to a second signal;
- a second loop filter for filtering a third signal;
- a comparator;
- a register coupled to the comparator;
- a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator;
- a delay circuit coupled to the register, for delaying an output signal of the register to form a delayed signal;
- a first path coupled between the register and the first loop filter, causing the delayed signal to be linearly combined with an input signal to form the first signal;
- and
- a second path coupled between the register and the second loop filter, causing the delayed signal to be linearly combined with the second signal to form the third signal.
6 more elements
A DSM comprising:
- a first loop filter for filtering a first signal to a second signal;
- a second loop filter for filtering a third signal;
- a comparator;
- a register coupled to the comparator;
- a first capacitor bank and a second capacitor bank parallelly coupled between the second loop filter and the comparator;
- a first back switch coupled between the first capacitor bank and an input of the comparator;
- a second back switch coupled between the second capacitor bank and the input of the comparator;
- a first path coupled between the register and the first loop filter, causing a delayed signal to be linearly combined with an input signal to form the first signal;
- and
- a second path coupled between the register and the second loop filter, causing the delayed signal to be linearly combined with the second signal to form the third signal;
- wherein:
- the delayed signal is formed by delaying an output signal of the register.
9 more elements
Dependencies are inferred from the claim text.