Analog-to-digital converters
AssigneeImec Vzw
InventorsEwout Martens, Benjamin Hershberg, Jan Craninckx
Life of this patent
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AssigneeImec Vzw
InventorsEwout Martens, Benjamin Hershberg, Jan Craninckx
Estimating the term…
A SAR DAC architecture is disclosed. In one aspect, the SAR DAC architecture uses two parallel DACs for performing a comparison and feedback simultaneously. While one DAC executes a feedback step, the output of the other DAC is used as input for a comparator. For fast operation, the comparator performs the comparison with a reference voltage that has a positive or negative offset from a mid-scale value. The sign of the offset is determined by a previous comparison step. As a result, the same delay can be used for each DAC feedback and comparison, reducing the total conversion time to the time needed for N comparisons for an N-bit architecture, which is a reduction of almost a factor of 2 compared to the conventional SAR architecture.
A successive approximation register (SAR) analog-to-digital architecture comprising:
An analog-to-digital converter (ADC) comprising:
A method of converting an analog signal to a digital signal, the method comprising:
Dependencies are inferred from the claim text.