Clock generating circuit and signal processing device

A signal processing device, comprising:

• a dividing unit that divides a reference clock to generate a divided clock, the divided clock having a frequency of 1/N times of a frequency of the reference clock, where N is an integer of two or more;
• a distribution unit that distributes the reference clock to a first route and a second route, the first route including an output terminal that outputs a clock with a frequency identical to the frequency of the reference clock, the second route including the dividing unit;
• and
• an analog/digital converter that performs an analog/digital conversion on a signal with a frequency between the frequency of the reference clock and the frequency of the divided clock based on the reference clock and the divided clock,
• wherein the dividing unit comprises:
• one or more amplifiers;
• one or more dividing circuits;
• and
• a correction circuit, disposed between the amplifier and the dividing circuit, the correction circuit corrects a level of an input clock input to the dividing circuit.