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US 10,483,976 B1Granted
Circuits to interpret pin inputs
AssigneeTexas Instruments Incorporated
InventorsJikai Chen, Yanli Fan
Life of this patent
Estimating the term…
Abstract
In examples, an apparatus comprises a pin, an input buffer coupled to the pin at an output of the input buffer, a voltage divider circuit coupled to the input buffer at an input of the input buffer, a first current mirror coupled to the input buffer, and a second current mirror coupled to the input buffer. The apparatus also comprises a first output buffer coupled between the input buffer and the first current mirror, and a second output buffer coupled between the input buffer and the second current mirror.
Claims12
An apparatus comprising:
- a pin;
- an input buffer coupled to the pin;
- a first current mirror coupled to the input buffer, the first current mirror comprising three transistors, each of the three transistors in the first current mirror coupling to a different one of three legs of the apparatus;
- a second current mirror coupled to the input buffer, the second current mirror comprising three transistors, each of the three transistors in the second current mirror coupling to a different one of the three legs of the apparatus;
- multiple level shifters positioned in a common leg of the three legs;
- a voltage divider circuit coupled to the multiple level shifters;
- a first output buffer coupled to the input buffer and the first current mirror;
- and
- a second output buffer coupled to the input buffer and the second current mirror.
6 more elements
An apparatus comprising:
- a pin;
- a first n-type metal oxide semiconductor field effect transistor (MOSFET) coupled to the pin;
- a first p-type MOSFET coupled to the pin;
- a second p-type MOSFET coupled to the first n-type MOSFET;
- a second n-type MOSFET coupled to the first p-type MOSFET;
- a third p-type MOSFET coupled to the second p-type MOSFET;
- a third n-type MOSFET coupled to the third p-type MOSFET and to the first n-type MOSFET;
- a fourth p-type MOSFET coupled to the third n-type MOSFET and to the first p-type MOSFET;
- a fourth n-type MOSFET coupled to the fourth p-type MOSFET and to the second n-type MOSFET;
- a fifth p-type MOSFET coupled to the second and third p-type MOSFETs;
- a fifth n-type MOSFET coupled to the second and fourth n-type MOSFETs;
- a voltage divider circuit comprising two resistors, a node between the resistors comprising a node between the third n-type MOSFET and the fourth p-type MOSFET;
- a first output buffer coupled to the first n-type MOSFET and the second p-type MOSFET;
- a second output buffer coupled to the first p-type MOSFET and the second n-type MOSFET;
- and
- a voltage source coupled to the second, third, and fifth p-type MOSFETs, wherein the second, fourth, and fifth n-type MOSFETs couple to ground.
13 more elements
An apparatus, comprising:
- a voltage source;
- a current mirror coupled to the voltage source;
- a voltage divider circuit coupled to the voltage source;
- multiple level shifters coupled to the voltage divider circuit;
- and
- two or more legs coupled to the current mirror and the multiple level shifters, each of the two or more legs comprising:
- a pin;
- a first n-type field effect transistor (FET) coupled to the pin;
- a first p-type FET coupled to the pin;
- a first output buffer coupled to the first n-type FET;
- a second output buffer coupled to the first p-type FET;
- a second p-type FET coupled to the first output buffer;
- and
- a second n-type FET coupled to the second output buffer.
11 more elements
Dependencies are inferred from the claim text.