Control circuit for controlling reset operation

A control circuit, comprising:

• a reset circuit coupled to a digital frequency divider of a phase locked loop circuit and configured to perform a reset operation;
• and
• a determination circuit coupled to the reset circuit and configured to determine whether a first predetermined time interval has elapsed so as to control the reset circuit to stop performing the reset operation when the first predetermined time interval has elapsed;
• wherein the phase locked loop circuit further comprises an analog frequency divider coupled to the digital frequency divider, and the first predetermined time interval corresponds to a time required for the analog frequency divider to stabilize;
• the determination circuit determines whether the first predetermined time interval has elapsed by counting;
• the phase locked loop circuit further comprises an oscillation source;
• the control circuit further comprises:
• an operation voltage generation circuit, comprising:
• an output terminal coupled to the analog frequency divider;
• and
• a first capacitor, comprising:
• a first terminal coupled to the output terminal of the operation voltage generation circuit;
• and
• a second terminal coupled to the oscillation source;
• the reset circuit comprises:
• an output terminal configured to perform the reset operation or stop the reset operation;
• and
• the first predetermined time interval corresponds to the time required for a voltage of the first terminal of the first capacitor to reach a ratio of a predetermined voltage;
• and
• the operation voltage generation circuit further comprises a bias voltage generator configured to provide a bias voltage to charge the first capacitor.