Phase interpolator, timing generator, and semiconductor integrated circuit

A semiconductor integrated circuit comprising:

• a set signal generator structured to generate a set signal;
• and
• a reset signal generator structured to generate a reset signal,
• wherein at least one from among the set signal generator and the reset signal generator comprises a timing generator, the timing generator comprising N (N≥2) stages,
• wherein an i-th (1≤i≤N−1) stage comprises a first phase interpolator and a second phase interpolator,
• wherein an output node of the first phase interpolator in the i-th (1≤i≤N−1) stage is coupled to a first input node of each of the first phase interpolator and the second interpolator in the (i+1)-th stage,
• wherein an output node of the second phase interpolator in the i-th stage is coupled to a second input node of each of the first phase interpolator and the second interpolator in the (i+1)-th stage,
• wherein the first phase interpolator and the second phase interpolator are each arranged such that a first signal is received via the first input node and such that a second signal is received via the second input node, and structured to generate an output signal having an edge at a timing that corresponds to control data,
• and wherein the first phase interpolator and the second phase interpolator each comprise a phase interpolator, the phase interpolator comprising:
• a first input node coupled to receive a first signal that transits from a first level to a second level;
• a second input node coupled to receive a second signal that transits from the first level to the second level with a delay with respect to the first signal;
• a first line coupled to receive a first voltage;
• a second line coupled to receive a second voltage;
• an intermediate line;
• a capacitor having one end coupled to the intermediate line;
• an initializing circuit structured to initialize a voltage across the capacitor during a period in which the first signal and the second signal are both set to the first level;
• a plurality of circuit units that correspond to a plurality of bits of an input code, and coupled in parallel between the intermediate line and the second line;
• and
• an output circuit structured to generate an output signal having a level that changes when the voltage across the capacitor crosses a predetermined threshold value,
• wherein each circuit unit comprises:
• a resistor and a first path arranged in series between the intermediate line and the second line;
• and
• a second path arranged in parallel with the first path,
• wherein the first path is structured such that, when the first signal is set to the second level and the corresponding bit of the input code is set to a first value, the first path is turned on,
• wherein the second path is structured such that, when the second signal is set to the second level and the corresponding bit of the input code is set to a second value, the second path is turned on,
• and wherein the semiconductor integrated circuit is structured to output a pulse signal that transits to a first level according to an output signal of the set signal generator, and that transits to a second level according to an output signal of the reset signal generator.