DC-DC converter

A DC-DC converter, comprising:

• a high potential input wiring connected to a positive electrode of a direct current source;
• a high potential output wiring;
• a low potential wiring connected to a negative electrode of the direct current source;
• a first lower FET of n-channel type, a source of the first lower FET being connected to the low potential wiring;
• a first upper FET of n-channel type, a source of the first upper FET being connected to a drain of the first lower FET, and a drain of the first upper FET being connected to the high potential output wiring;
• a second lower FET of n-channel type, a source of the second lower FET being connected to the low potential wiring;
• a second upper FET of n-channel type, a source of the second upper FET being connected to a drain of the second lower FET, and a drain of the second upper FET being connected to the high potential output wiring;
• a first diode, an anode of the first diode being connected to the source of the first upper FET, and a cathode of the first diode being connected to the drain of the first upper FET;
• a second diode, an anode of the second diode being connected to the source of the second upper FET, and a cathode of the second diode being connected to the drain of the second upper FET;
• a main reactor comprising a first terminal and a second terminal, the first terminal being connected to the high potential input wiring;
• a first sub-reactor, one end of the first sub-reactor being connected to the second terminal of the main reactor, and other end of the first sub-reactor being connected to the drain of the first lower FET;
• a second sub-reactor, one end of the second sub-reactor being connected to the second terminal of the main reactor, and other end of the second sub-reactor being connected to the drain of the second lower FET;
• and
• a gate controller connected to a gate of the first lower FET, a gate of the first upper FET, a gate of the second lower FET, and a gate of the second upper FET, wherein
• the gate controller is configured to perform a first operation and a second operation based on a variable current flowing through the main reactor,
• the gate controller is configured to perform the first operation during a zero-cross mode in which the variable current decreases to zero, and to perform the second operation during a non-zero-cross mode in which the variable current does not decrease to zero,
• in the first operation, the gate controller controls the first lower FET, the first upper FET, the second lower FET, and the second upper FET so as to satisfy following conditions:
• a first state, a second state, a third state, and a fourth state repeatedly appear in this order, the first state being a state in which the first lower FET is on, the second state being a state in which the first lower FET and the second lower FET are off, the third state being a state in which the second lower FET is on, and the fourth state being a state in which the first lower FET and the second lower FET are off;
• and
• the first upper FET and the second upper FET are not turned on,
• in the second operation, the gate controller controls the first lower FET, the first upper FET, the second lower FET, and the second upper FET so as to satisfy following conditions:
• a fifth state, a sixth state, a seventh state, and an eighth state repeatedly appear in this order, the fifth state being a state in which the first lower FET is on and the second lower FET is off, the sixth state being a state in which the first lower FET and the second lower FET are off, the seventh state being a state in which the first lower FET is off and the second lower FET is on, and the eighth state being a state in which the first lower FET and the second lower FET are off;
• and
• the first upper FET is turned on in at least a part of a period of the sixth state, and the second upper FET is turned on in at least a part of a period of the eighth state.