Fast memory access control for phase and gain

A method for fast memory access control, comprising the steps of:

• buffering a plurality of setting values received from a memory in a plurality of registers hardwired as a plurality of subsets;
• generating a sequence of pulses in a plurality of control signals in response to a plurality of cycles of an enable signal_, wherein a single one of said pulses is generated in a single one of said control signals at a time during each of said cycles of said enable signal;
• and
• presenting said setting values from a single one of said subsets of said registers to a plurality of transceiver circuits while a corresponding one of said control signals is in an active state, wherein said transceiver circuits are updated with said setting values from said registers within a predetermined time.

An apparatus comprising:

• a switching circuit configured to generate a sequence of pulses in a plurality of control signals in response to a plurality of cycles of an enable signal;
• a plurality of first registers hardwired as a plurality of subsets, wherein (i) each of said subsets of said first registers is configured to (a) buffer a plurality of setting values received from a memory and (b) present said setting values from said registers to a plurality of transceiver circuits while a corresponding one of said control signals is in an active state, and (ii) said transceiver circuits are updated with said setting values from said registers within a predetermined time;
• and
• a plurality of second registers configured to (i) buffer a plurality of bias values and (ii) present said bias values to said transceiver circuits, wherein said bias values trim said transceiver circuits without steering a radio frequency beam generated by said transceiver circuits.