US 10,483,404 B2Granted

Thin film transistor with multiple oxide semiconductor layers

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorShunpei Yamazaki

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Abstract

A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity.

Claims13

Dependent claims

A semiconductor device comprising:

a first oxide semiconductor layer comprising indium and gallium;
a second oxide semiconductor layer comprising indium and gallium over the first oxide semiconductor layer;
a third oxide semiconductor layer comprising indium and gallium over the second oxide semiconductor layer;
a gate insulating layer over the third oxide semiconductor layer;
and
a gate electrode over the gate insulating layer,
wherein a content of the gallium in the first oxide semiconductor layer is higher than a content of the indium in the first oxide semiconductor layer,
wherein a content of the indium in the second oxide semiconductor layer is higher than a content of the gallium in the second oxide semiconductor layer,
wherein a content of the gallium in the third oxide semiconductor layer is higher than a content of the indium in the third oxide semiconductor layer,
wherein a proportion of the indium to the gallium in the first oxide semiconductor layer is lower than a proportion of the indium to the gallium in the third oxide semiconductor layer, and
wherein the second oxide semiconductor layer comprises a region which is not overlapped with the gate electrode and comprises at least one of nitrogen, argon, and aluminum.

8 more elements

A semiconductor device comprising:

a first oxide semiconductor layer comprising indium and gallium;
a second oxide semiconductor layer comprising indium and gallium over the first oxide semiconductor layer;
a third oxide semiconductor layer comprising indium and gallium over the second oxide semiconductor layer;
a first insulating layer over the third oxide semiconductor layer;
a gate electrode over the first insulating layer, and
a second insulating layer in contact with a side surface of the gate electrode,
wherein a content of the gallium in the first oxide semiconductor layer is higher than a content of the indium in the first oxide semiconductor layer,
wherein a content of the indium in the second oxide semiconductor layer is higher than a content of the gallium in the second oxide semiconductor layer,
wherein a content of the gallium in the third oxide semiconductor layer is higher than a content of the indium in the third oxide semiconductor layer,
wherein a proportion of the indium to the gallium in the first oxide semiconductor layer is lower than a proportion of the indium to the gallium in the third oxide semiconductor layer, and
wherein the second oxide semiconductor layer comprises a region which is not overlapped with the gate electrode and the second insulating layer and comprises at least one of nitrogen, argon, and aluminum.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/039,531Filed 19 Jul 2018 · continuation
Priority: JP 2012-13643815 Jun 2012
Published: US 2018/0323308 A18 Nov 2018
Granted: 19 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 30/6755
Characterised by the active materials: oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
H10D 30/615
Having multiple independently-addressable gate electrodes influencing the same channel: comprising a MOS gate electrode and at least one non-MOS…
H10D 30/67
Insulated-gate field-effect transistors [IGFET]: thin-film transistors [TFT]
H10D 30/6757
Thin-film transistors [TFT]: characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile

Family

Application13/916,167Parent of this continuation · filed 12 Jun 2013
Application14/873,279Parent of this continuation · filed 2 Oct 2015
US 9,153,699 B2Parent of this continuation · filed 6 Oct 2015
Application15/244,104Parent of this continuation · filed 23 Aug 2016
US 9,437,747 B2Parent of this continuation · filed 6 Sep 2016
US 2018/0323308 A1Pre-grant publication · published 8 Nov 2018
US 10,032,926 B2Parent of this continuation
US 2013/0334533 A1Published application
US 2016/0027923 A1Published application
US 2016/0359051 A1Published application
US 10,483,404 B2This patent

From the US filing history. Foreign family members aren’t listed.

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