US 10,483,397 B2Granted

Fin field effect transistor and method of forming the same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsJu-Wang Hsu, Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai

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Abstract

A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.

Claims20

Dependent claims

A fin field effect transistor, comprising:

a semiconductor substrate having a fin structure between two trenches, wherein each of the two trenches has a top portion and a bottom portion, the top portion of each of the two trenches is closer to a top portion of the fin structure than the bottom portion of each of the two trenches;
shallow trench isolations respectively formed in the bottom portions of the two trenches, wherein the top portion of the fin structure is tapered and above the shallow trench isolations;
a gate electrode over the fin structure and the shallow trench isolations, wherein the gate electrode is perpendicular to the fin structure;
a gate dielectric layer along sidewalls of the fin structure;
and
a source/drain doped region formed in the fin structure,
wherein each of the shallow trench isolations has a rounded and convex top corner, a rounded and convex bottom corner and a straight side edge,
wherein the rounded and convex top corner of each of the shallow trench isolations is close to and separated from the fin structure,
wherein the rounded and convex bottom corner of each of the shallow trench isolations is in contact with the bottom portion of each of the two trenches,
wherein the rounded and convex top corner of each of the shallow trench isolations is directly connected the straight side edge of each of the shallow trench isolations, and the shallow trench isolations are in contact with the fin structure,
wherein the gate dielectric layer has a convex top surface and a concave bottom surface, and an entirety of the gate dielectric layer is disposed at a level between a top surface of the fin structure and the rounded and convex top corner of each of the shallow trench isolations.

8 more elements

A fin field effect transistor, comprising:

a semiconductor substrate having a fin structure between two trenches, wherein each of the two trenches has a top portion and a bottom portion, the top portion of each of the two trenches is closer to a top portion of the fin structure than the bottom portion of each of the two trenches;
shallow trench isolations respectively formed in the bottom portions of the two trenches;
a gate electrode over the fin structure and the shallow trench isolations, wherein a top surface of the fin structure is separated from the gate electrode by a first distance;
a mask layer between the top surface of the fin structure and the gate electrode, wherein the mask layer comprises silicon oxycarbide;
a gate dielectric layer along sidewalls of the fin structure, wherein the sidewalls of the fin structure are separated from the gate electrode by a second distance;
and
a source/drain doped region formed in the fin structure,
wherein one of the shallow trench isolations is in one of the two trenches and has a rounded and convex top corner, a rounded and convex bottom corner and a straight side edge,
wherein the rounded and convex top corner of the one of the shallow trench isolations is formed without extending into the fin structure,
wherein the rounded and convex top corner and the rounded and convex bottom corner are connected by the straight side edge of the one of the shallow trench isolations, wherein the straight side edge of the one of the shallow trench isolations is in contact with one of the sidewalls of the fin structure,
wherein the gate dielectric layer has a curved top surface and a curved bottom surface and is entirely disposed at a level between the top surface of the fin structure and the rounded and convex top corner.

8 more elements

A fin field effect transistor, comprising:

a semiconductor substrate having a fin structure between two trenches, wherein each of the two trenches has a top portion and a bottom portion, the top portion of each of the two trenches is closer to a top portion of the fin structure than the bottom portion of each of the two trenches;
shallow trench isolations respectively formed in the bottom portions of the two trenches, wherein the top portion of the fin structure is above the shallow trench isolations, and a maximum bottom width of the top portion of the fin structure is greater than a maximum top width of the top portion of the fin structure;
a gate electrode over the fin structure and the shallow trench isolations, wherein the top surface of the fin structure is separated from the gate electrode by a first oxide layer and a mask layer, and sidewalls of the fin structure are separated from the gate electrode by a second oxide layer, wherein the mask layer is made of silicon oxycarbide;
and
a source/drain doped region formed in the fin structure,
wherein each of the shallow trench isolations has a rounded and convex bottom corner, a rounded and convex top corner, a straight side edge and a straight bottom edge,
wherein the rounded and convex top corner of each of the shallow trench isolations is formed without extending into the fin structure,
wherein the rounded and convex bottom corner of one of the shallow trench isolations in one of the two trenches extends between a first end and a second end, the first end is joined by the straight side edge of the one of the shallow trench isolations, and the second end is joined by the straight bottom edge of the one of the shallow trench isolations, and
wherein the straight side edge and the straight bottom edge of the one of the shallow trench isolations are in contact with the bottom portion of the one of the two trenches,
wherein the second oxide layer has a convex surface at a first end close to a top surface of the fin structure and a concave surface at a second end close to the rounded and convex top corner of each of the shallow trench isolations, and an entirety of the second oxide layer is disposed at a level between the top surface of the fin structure and the rounded and convex top corner of each of the shallow trench isolations.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/582,576Filed 24 Dec 2014 · division
Priority: 7 May 2007
Published: US 2015/0137265 A121 May 2015
Granted: 19 Nov 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 30/6211
Fin field-effect transistors [FinFET]: having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 62/115
Isolations within a component, i.e. internal isolations: dielectric isolations, e.g. air gaps
H10D 30/6212
Fin field-effect transistors [FinFET]: having fin-shaped semiconductor bodies having non-rectangular cross-sections

Family

Application11/744,896Parent of this division · filed 7 May 2007
US 2015/0137265 A1Pre-grant publication · published 21 May 2015
US 8,927,353 B2Parent of this division
US 2008/0277745 A1Published application
US 10,483,397 B2This patent

From the US filing history. Foreign family members aren’t listed.

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