Capacitive tuning using backside gate

A method of constructing a balanced radio frequency (RF) integrated circuit (RFIC) including a stack of switch multi-finger transistors, comprising:

• fabricating a first dual gate transistor having a first gate with a first gate length on a first side of a substrate supported by a sacrificial substrate;
• fabricating a second dual gate transistor having a third gate with a third gate length on the first side of the substrate and adjacent to the first dual gate transistor;
• depositing a first side dielectric layer on the first dual gate transistor and the second dual gate transistor;
• bonding a handle substrate to the first side dielectric layer;
• removing the sacrificial substrate;
• fabricating a second gate, with a second gate length, of the first dual gate transistor on a second side opposite the first side of the substrate and overlapping with the first gate;
• fabricating a fourth gate, with a fourth gate length, of the second dual gate transistor on the second side of the substrate and overlapping with the third gate, in which the second gate length is different than the fourth gate length;
• and
• depositing a dielectric layer on the second side of the substrate and in contact with the second gate and the fourth gate.